{"id":"https://openalex.org/W4242653592","doi":"https://doi.org/10.1109/date.2012.6176712","title":"Modeling and design exploration of FBDRAM as on-chip memory","display_name":"Modeling and design exploration of FBDRAM as on-chip memory","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W4242653592","doi":"https://doi.org/10.1109/date.2012.6176712"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176712","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176712","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101850376","display_name":"Guangyu Sun","orcid":"https://orcid.org/0000-0001-6436-0820"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Guangyu Sun","raw_affiliation_strings":["Center for Energy-efficient Computing and Applications, School of EECS, Peking University, China"],"affiliations":[{"raw_affiliation_string":"Center for Energy-efficient Computing and Applications, School of EECS, Peking University, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100688536","display_name":"Cong Xu","orcid":"https://orcid.org/0000-0002-5426-9721"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cong Xu","raw_affiliation_strings":["Computer Science and Engineering, Pennsylvania State University, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Computer Science and Engineering, Pennsylvania State University, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101850376"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.36462432,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1507","last_page":"1512"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7730756998062134},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7207463383674622},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6471671462059021},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5409828424453735},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5407649278640747},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5327686667442322},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.48921942710876465},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4738609790802002},{"id":"https://openalex.org/keywords/obstacle","display_name":"Obstacle","score":0.4544215798377991},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4430548846721649},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44123515486717224},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40321409702301025},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.37172335386276245},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3224574327468872},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26866739988327026},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.26210522651672363},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.22239768505096436},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.22224187850952148},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1877879500389099},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14997068047523499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1149049699306488}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7730756998062134},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7207463383674622},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6471671462059021},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5409828424453735},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5407649278640747},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5327686667442322},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48921942710876465},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4738609790802002},{"id":"https://openalex.org/C2776650193","wikidata":"https://www.wikidata.org/wiki/Q264661","display_name":"Obstacle","level":2,"score":0.4544215798377991},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4430548846721649},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44123515486717224},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40321409702301025},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.37172335386276245},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3224574327468872},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26866739988327026},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26210522651672363},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.22239768505096436},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.22224187850952148},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1877879500389099},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14997068047523499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1149049699306488},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2012.6176712","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176712","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-133691","is_oa":false,"landing_page_url":"http://gateway.isiknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=LinksAMR&SrcApp=PARTNER_APP&DestLinkType=FullRecord&DestApp=WOS&KeyUT=000415126300287","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1497430048","https://openalex.org/W2038423440","https://openalex.org/W2102522641","https://openalex.org/W2103904887","https://openalex.org/W2110149201","https://openalex.org/W2113613740","https://openalex.org/W2122435992","https://openalex.org/W2126112620","https://openalex.org/W2162566384","https://openalex.org/W2169170787","https://openalex.org/W2169875292","https://openalex.org/W4254506919","https://openalex.org/W6676495747","https://openalex.org/W6676818422"],"related_works":["https://openalex.org/W2516517078","https://openalex.org/W1974599144","https://openalex.org/W2150909864","https://openalex.org/W3146763006","https://openalex.org/W4382618825","https://openalex.org/W2161286015","https://openalex.org/W2127643145","https://openalex.org/W2189053673","https://openalex.org/W2186356227","https://openalex.org/W4319596555"],"abstract_inverted_index":{"Compared":[0],"to":[1,44,65,88,105],"the":[2,30,81,90,110,123],"traditional":[3,31,133],"DRAM":[4,8],"technology,":[5],"floating":[6],"body":[7],"(FBDRAM)":[9],"has":[10,61],"many":[11],"advantages,":[12],"such":[13],"as":[14,47],"high":[15],"density,":[16],"fast":[17],"access":[18],"speed,":[19],"long":[20],"retention":[21],"time,":[22],"etc.":[23],"More":[24],"important,":[25],"FBDRAM":[26,36,78,106,128],"is":[27],"compatible":[28],"with":[29,80,132],"CMOS":[32],"technology.":[33],"It":[34],"makes":[35],"more":[37],"competitive":[38],"than":[39],"other":[40],"emerging":[41],"memory":[42,54],"technologies":[43],"be":[45],"employed":[46],"on-chip":[48],"memory.":[49],"The":[50],"characteristic":[51],"variance":[52],"of":[53,77,83,92],"cells":[55],"caused":[56],"by":[57],"process":[58,84,93],"variations,":[59,94],"however,":[60],"become":[62],"an":[63],"obstacle":[64],"adopt":[66],"FBDRAM.":[67],"In":[68,86],"this":[69,119],"work,":[70],"we":[71,95,121],"build":[72],"a":[73],"circuit":[74,138],"level":[75],"model":[76],"caches":[79,107,135],"consideration":[82],"variations.":[85],"order":[87],"mitigate":[89],"impact":[91],"apply":[96],"different":[97],"error":[98],"correction":[99],"mechanisms":[100],"and":[101,108,116,129,139],"corresponding":[102],"architecture-level":[103],"modifications":[104],"study":[109],"trade-off":[111],"among":[112],"reliability,":[113],"power":[114],"consumption,":[115],"performance.":[117],"With":[118],"model,":[120],"explore":[122],"L2":[124],"cache":[125],"design":[126],"using":[127],"compare":[130],"it":[131],"SRAM/eDRAM":[134],"in":[136],"both":[137],"architectural":[140],"levels":[141],"<sup":[142],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[143],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sup>":[144],".":[145]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}