{"id":"https://openalex.org/W4249416173","doi":"https://doi.org/10.1109/date.2012.6176673","title":"3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs","display_name":"3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W4249416173","doi":"https://doi.org/10.1109/date.2012.6176673"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100722125","display_name":"Yibo Chen","orcid":"https://orcid.org/0000-0001-6054-207X"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yibo Chen","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066056671","display_name":"Guangyu Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangyu Sun","raw_affiliation_strings":["Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029272799","display_name":"Qiaosha Zou","orcid":"https://orcid.org/0000-0001-6662-4316"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qiaosha Zou","raw_affiliation_strings":["Pennsylvania State University, University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Pennsylvania State University, University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100722125"],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.654353,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1185","last_page":"1190"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9025453329086304},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.8175269365310669},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6295891404151917},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.615521252155304},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5748740434646606},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5383983254432678},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.5026688575744629},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4919590651988983},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.47991761565208435},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.47015997767448425},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.461561381816864},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46131181716918945},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4576607346534729},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4478687047958374},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4299986958503723},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41794970631599426},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41638848185539246},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4115082919597626},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.41074222326278687},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30118557810783386},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26921093463897705},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1452890932559967},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13658013939857483},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.12774613499641418}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9025453329086304},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.8175269365310669},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6295891404151917},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.615521252155304},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5748740434646606},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5383983254432678},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.5026688575744629},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4919590651988983},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.47991761565208435},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.47015997767448425},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.461561381816864},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46131181716918945},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4576607346534729},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4478687047958374},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4299986958503723},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41794970631599426},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41638848185539246},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4115082919597626},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.41074222326278687},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30118557810783386},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26921093463897705},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1452890932559967},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13658013939857483},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.12774613499641418},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2012.6176673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.4399999976158142,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1506241038","https://openalex.org/W1987131925","https://openalex.org/W2023264348","https://openalex.org/W2061048687","https://openalex.org/W2098204276","https://openalex.org/W2121318787","https://openalex.org/W2129960401","https://openalex.org/W2158921969","https://openalex.org/W3149637621","https://openalex.org/W4239130802","https://openalex.org/W4247816723","https://openalex.org/W4253343649","https://openalex.org/W4254506919","https://openalex.org/W4255374779","https://openalex.org/W6666095544","https://openalex.org/W6675804706","https://openalex.org/W6680900816","https://openalex.org/W6681420791"],"related_works":["https://openalex.org/W1965050610","https://openalex.org/W1990789187","https://openalex.org/W2994788014","https://openalex.org/W2809933636","https://openalex.org/W2005457717","https://openalex.org/W2001838379","https://openalex.org/W4211105560","https://openalex.org/W2074570708","https://openalex.org/W1525696892","https://openalex.org/W1541633348"],"abstract_inverted_index":{"Three-dimensional":[0],"(3D)":[1],"circuit":[2,114],"integration":[3],"is":[4,27,56,102,134],"a":[5,105],"promising":[6],"technology":[7],"to":[8,38,58,107,110,147],"alleviate":[9],"performance":[10],"and":[11,92,138],"power":[12],"related":[13],"issues":[14],"raised":[15],"by":[16,52,136,144],"interconnects":[17],"in":[18],"nanometer":[19],"CMOS.":[20],"Physical":[21],"planning":[22,119],"of":[23,32,41,44,66,86,96,113],"three-dimensional":[24,53],"integrated":[25,35],"circuits":[26],"substantially":[28],"different":[29],"from":[30],"that":[31,81,124],"traditional":[33],"planar":[34],"circuits,":[36],"due":[37],"the":[39,48,67,89,117,126,130,139,148],"presence":[40],"multiple":[42],"layers":[43],"dies.":[45],"To":[46],"realize":[47],"full":[49],"potential":[50],"offered":[51],"integration,":[54],"it":[55],"necessary":[57],"take":[59],"physical":[60,118],"information":[61],"into":[62,88],"consideration":[63],"at":[64],"higher-levels":[65],"design":[68],"abstraction":[69],"for":[70],"3D":[71,97],"ICs.":[72],"This":[73],"paper":[74],"proposes":[75],"an":[76],"incremental":[77],"system-level":[78],"synthesis":[79,85,101],"framework":[80],"tightly":[82],"integrates":[83],"behavioral":[84],"modules":[87,115],"layer":[90],"assignment":[91],"floorplan-":[93],"ning":[94],"stage":[95],"IC":[98],"design.":[99],"Behavioral":[100],"implemented":[103],"as":[104],"sub-routine":[106],"be":[108],"called":[109],"adjust":[111],"delay/power/variability/area":[112],"during":[116],"process.":[120],"Experimental":[121],"results":[122],"show":[123],"with":[125],"proposed":[127],"synthesis-during-planning":[128],"methodology,":[129],"overall":[131],"timing":[132],"yield":[133],"improved":[135],"8%,":[137],"chip":[140],"peak":[141],"temperature":[142],"reduced":[143],"6.6\u00b0C,":[145],"compared":[146],"conventional":[149],"planning-after-synthesis":[150],"approach.":[151]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
