{"id":"https://openalex.org/W3146749039","doi":"https://doi.org/10.1109/date.2012.6176663","title":"Exploring pausible clocking based GALS design for 40-nm system integration","display_name":"Exploring pausible clocking based GALS design for 40-nm system integration","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W3146749039","doi":"https://doi.org/10.1109/date.2012.6176663","mag":"3146749039"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176663","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034733719","display_name":"Xin Fan","orcid":"https://orcid.org/0000-0001-6954-5074"},"institutions":[{"id":"https://openalex.org/I92894754","display_name":"Innovations for High Performance Microelectronics","ror":"https://ror.org/0489gab80","country_code":"DE","type":"facility","lineage":["https://openalex.org/I315704651","https://openalex.org/I92894754"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Xin Fan","raw_affiliation_strings":["IHP Microelectronics, Frankfurt, Germany"],"affiliations":[{"raw_affiliation_string":"IHP Microelectronics, Frankfurt, Germany","institution_ids":["https://openalex.org/I92894754"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004959402","display_name":"Milo\u0161 Krsti\u0107","orcid":"https://orcid.org/0000-0003-0267-0203"},"institutions":[{"id":"https://openalex.org/I92894754","display_name":"Innovations for High Performance Microelectronics","ror":"https://ror.org/0489gab80","country_code":"DE","type":"facility","lineage":["https://openalex.org/I315704651","https://openalex.org/I92894754"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Krstic","raw_affiliation_strings":["IHP Microelectronics, Frankfurt, Germany"],"affiliations":[{"raw_affiliation_string":"IHP Microelectronics, Frankfurt, Germany","institution_ids":["https://openalex.org/I92894754"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053247434","display_name":"Eckhard Grass","orcid":"https://orcid.org/0000-0002-9718-4170"},"institutions":[{"id":"https://openalex.org/I92894754","display_name":"Innovations for High Performance Microelectronics","ror":"https://ror.org/0489gab80","country_code":"DE","type":"facility","lineage":["https://openalex.org/I315704651","https://openalex.org/I92894754"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"E. Grass","raw_affiliation_strings":["IHP Microelectronics, Frankfurt, Germany"],"affiliations":[{"raw_affiliation_string":"IHP Microelectronics, Frankfurt, Germany","institution_ids":["https://openalex.org/I92894754"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062342929","display_name":"Beverly A. Sanders","orcid":"https://orcid.org/0000-0003-4010-0623"},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"B. Sanders","raw_affiliation_strings":["Intel Mobile Communications, Neubiberg, Germany"],"affiliations":[{"raw_affiliation_string":"Intel Mobile Communications, Neubiberg, Germany","institution_ids":["https://openalex.org/I4210094487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049263798","display_name":"C. Heer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"C. Heer","raw_affiliation_strings":["Intel Mobile Communications, Neubiberg, Germany"],"affiliations":[{"raw_affiliation_string":"Intel Mobile Communications, Neubiberg, Germany","institution_ids":["https://openalex.org/I4210094487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5034733719"],"corresponding_institution_ids":["https://openalex.org/I92894754"],"apc_list":null,"apc_paid":null,"fwci":0.3546,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69261907,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1118","last_page":"1121"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7419032454490662},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6551720499992371},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6081919074058533},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5940242409706116},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5760340690612793},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.525391161441803},{"id":"https://openalex.org/keywords/baseband","display_name":"Baseband","score":0.4718192517757416},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47097277641296387},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.44796329736709595},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4274980127811432},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4264844059944153},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4177754819393158},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.413308322429657},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33994555473327637},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2627825438976288},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.15955686569213867},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.13967472314834595},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13825377821922302}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7419032454490662},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6551720499992371},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6081919074058533},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5940242409706116},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5760340690612793},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.525391161441803},{"id":"https://openalex.org/C65165936","wikidata":"https://www.wikidata.org/wiki/Q575784","display_name":"Baseband","level":3,"score":0.4718192517757416},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47097277641296387},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.44796329736709595},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4274980127811432},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4264844059944153},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4177754819393158},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.413308322429657},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33994555473327637},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2627825438976288},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.15955686569213867},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.13967472314834595},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13825377821922302},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2012.6176663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176663","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1609287256","https://openalex.org/W1943426535","https://openalex.org/W2027363446","https://openalex.org/W2101113282","https://openalex.org/W2102742603","https://openalex.org/W2111172002","https://openalex.org/W2117897741","https://openalex.org/W2160823654","https://openalex.org/W4246334093","https://openalex.org/W4254596596","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W2055430327","https://openalex.org/W53262038","https://openalex.org/W2169248084","https://openalex.org/W1976012348","https://openalex.org/W1973069902","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W2051542972","https://openalex.org/W4230718388","https://openalex.org/W2047284788"],"abstract_inverted_index":{"Globally":[0],"asynchronous":[1],"locally":[2],"synchronous":[3,118],"(GALS)":[4],"design":[5,19,78],"has":[6],"attracted":[7],"intensive":[8],"research":[9],"attention":[10],"during":[11],"the":[12,16,21,31,42,55,61,82,107,117,134],"last":[13],"decade.":[14],"Among":[15],"existing":[17],"GALS":[18,51,73,77,135],"solutions,":[20],"pausible":[22,45,83],"clocking":[23,46,84],"scheme":[24,47,85],"presents":[25],"an":[26],"elegant":[27],"solution":[28],"to":[29,116],"address":[30],"cross-clock":[32],"synchronization":[33],"issues":[34],"with":[35],"low":[36],"hardware":[37],"overhead.":[38],"This":[39],"work":[40],"explored":[41],"applications":[43],"of":[44,57],"for":[48,72],"area/power":[49],"efficient":[50],"design.":[52,74],"To":[53],"alleviate":[54],"challenge":[56],"timing":[58],"convergence":[59],"at":[60],"system":[62,68],"level,":[63],"area":[64,124],"and":[65,104,125],"power":[66,129],"balanced":[67],"partitioning":[69],"was":[70,86,101],"applied":[71],"An":[75],"optimized":[76],"flow":[79],"based":[80],"on":[81],"further":[87],"proposed.":[88],"As":[89],"a":[90,93],"practical":[91],"example,":[92],"synchronous/GALS":[94],"OFDM":[95],"baseband":[96],"transmitter":[97],"chip,":[98],"named":[99],"Moonrake,":[100],"then":[102],"designed":[103],"fabricated":[105],"using":[106],"40-nm":[108],"CMOS":[109],"process.":[110],"It":[111],"is":[112],"shown":[113],"that,":[114],"compared":[115],"baseline":[119],"design,":[120],"5%":[121],"reduction":[122],"in":[123,128,133],"6%":[126],"saving":[127],"can":[130],"be":[131],"achieved":[132],"counterpart.":[136]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
