{"id":"https://openalex.org/W4249791697","doi":"https://doi.org/10.1109/date.2012.6176628","title":"Transistor-level gate model based statistical timing analysis considering correlations","display_name":"Transistor-level gate model based statistical timing analysis considering correlations","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W4249791697","doi":"https://doi.org/10.1109/date.2012.6176628"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008743951","display_name":"Qin Tang","orcid":"https://orcid.org/0000-0001-9296-4074"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Qin Tang","raw_affiliation_strings":["Circuits and Systems, Delft University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems, Delft University of Technology, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087760502","display_name":"A. Zjajo","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"A. Zjajo","raw_affiliation_strings":["Circuits and Systems, Delft University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems, Delft University of Technology, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059391032","display_name":"M. Berkelaar","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"M. Berkelaar","raw_affiliation_strings":["Circuits and Systems, Delft University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems, Delft University of Technology, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021292650","display_name":"Nick van der Meijs","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"N. van der Meijs","raw_affiliation_strings":["Circuits and Systems, Delft University of Technology, Netherlands"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems, Delft University of Technology, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5008743951"],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65438119,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"917","last_page":"922"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6757194399833679},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6511569023132324},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5814729928970337},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5701836347579956},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5635735988616943},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5467754602432251},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5226290225982666},{"id":"https://openalex.org/keywords/statistical-model","display_name":"Statistical model","score":0.5068345665931702},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.4947011172771454},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.4855498969554901},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.4568134546279907},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4487650394439697},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3917604088783264},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1242741048336029},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11474558711051941},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11073485016822815},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.09526854753494263}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6757194399833679},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6511569023132324},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5814729928970337},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5701836347579956},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5635735988616943},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5467754602432251},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5226290225982666},{"id":"https://openalex.org/C114289077","wikidata":"https://www.wikidata.org/wiki/Q3284399","display_name":"Statistical model","level":2,"score":0.5068345665931702},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.4947011172771454},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.4855498969554901},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.4568134546279907},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4487650394439697},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3917604088783264},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1242741048336029},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11474558711051941},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11073485016822815},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.09526854753494263},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2012.6176628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1963923972","https://openalex.org/W1968992562","https://openalex.org/W2086855053","https://openalex.org/W2106251971","https://openalex.org/W2120039313","https://openalex.org/W2133970570","https://openalex.org/W2142202849","https://openalex.org/W2154680820","https://openalex.org/W2164208726","https://openalex.org/W4231444968","https://openalex.org/W4237437637","https://openalex.org/W4289256183","https://openalex.org/W6684286881"],"related_works":["https://openalex.org/W1980349267","https://openalex.org/W1513105280","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2151104031","https://openalex.org/W2765435638","https://openalex.org/W2766377030","https://openalex.org/W2130189791","https://openalex.org/W2121863912"],"abstract_inverted_index":{"To":[0],"increase":[1],"the":[2,8,18,26,124],"accuracy":[3,70,126],"of":[4,28,129],"static":[5],"timing":[6,35,49],"analysis,":[7],"traditional":[9],"nonlinear":[10],"delay":[11],"models":[12,23,32],"(NLDMs)":[13],"are":[14,65,73,92],"increasingly":[15],"replaced":[16],"by":[17],"more":[19],"physical":[20],"current":[21],"source":[22],"(CSMs).":[24],"However,":[25],"extension":[27],"CSMs":[29],"into":[30],"statistical":[31,34,48,76],"for":[33],"analysis":[36,50],"is":[37,104],"not":[38],"easy.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"propose":[44],"a":[45,82,117],"novel":[46],"correlation-preserving":[47],"method":[51],"based":[52],"on":[53],"transistor-level":[54,77],"gate":[55,78],"models.":[56],"The":[57,69,89,101,121],"correlations":[58],"among":[59],"signals":[60],"and":[61,71,98,112,127],"between":[62],"process":[63],"variations":[64],"fully":[66],"accounted":[67],"for.":[68],"efficiency":[72],"obtained":[74],"from":[75],"models,":[79],"evaluated":[80],"using":[81],"smart":[83],"Random":[84],"Differential":[85],"Equation":[86],"(RDE)-based":[87],"solver.":[88],"variational":[90],"waveforms":[91],"available,":[93],"allowing":[94],"signal":[95],"integrity":[96],"checks":[97],"circuit":[99],"optimization.":[100],"proposed":[102],"algorithm":[103],"verified":[105],"with":[106],"standard":[107],"cells,":[108],"simple":[109],"digital":[110],"circuits":[111,115],"ISCAS":[113],"benchmark":[114],"in":[116],"45":[118],"nm":[119],"technology.":[120],"results":[122],"demonstrate":[123],"high":[125],"speed":[128],"our":[130],"algorithm.":[131]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
