{"id":"https://openalex.org/W4236677774","doi":"https://doi.org/10.1109/date.2012.6176622","title":"A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories","display_name":"A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W4236677774","doi":"https://doi.org/10.1109/date.2012.6176622"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084809231","display_name":"Cristian Zambelli","orcid":"https://orcid.org/0000-0001-8755-0504"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"C. Zambelli","raw_affiliation_strings":["Engineering Department, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034809609","display_name":"Marco Indaco","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Indaco","raw_affiliation_strings":["Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021242722","display_name":"M. Fabiano","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Fabiano","raw_affiliation_strings":["Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026593274","display_name":"Stefano Di Carlo","orcid":"https://orcid.org/0000-0002-7512-5356"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Di Carlo","raw_affiliation_strings":["Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036258272","display_name":"P. Prinetto","orcid":"https://orcid.org/0000-0003-2400-8245"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Prinetto","raw_affiliation_strings":["Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069964414","display_name":"P. Olivo","orcid":"https://orcid.org/0000-0002-8751-4666"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Olivo","raw_affiliation_strings":["Engineering Department, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072823735","display_name":"D. Bertozzi","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Bertozzi","raw_affiliation_strings":["Engineering Department, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5084809231"],"corresponding_institution_ids":["https://openalex.org/I201324441"],"apc_list":null,"apc_paid":null,"fwci":3.03227084,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.91820969,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"881","last_page":"886"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7567806243896484},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6708803772926331},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5438268184661865},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5398696064949036},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5321483016014099},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.5284654498100281},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.5177232623100281},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.48758524656295776},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.47859832644462585},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.4772631824016571},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.45131444931030273},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3401830792427063},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24344760179519653},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21459320187568665},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15639081597328186},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09512591361999512}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7567806243896484},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6708803772926331},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5438268184661865},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5398696064949036},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5321483016014099},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.5284654498100281},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.5177232623100281},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.48758524656295776},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.47859832644462585},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.4772631824016571},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.45131444931030273},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3401830792427063},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24344760179519653},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21459320187568665},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15639081597328186},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09512591361999512},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2012.6176622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/1563462","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/1563462","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1767399337","https://openalex.org/W2017159197","https://openalex.org/W2095342970","https://openalex.org/W2097471282","https://openalex.org/W2101380322","https://openalex.org/W2103879481","https://openalex.org/W2107450441","https://openalex.org/W2109190450","https://openalex.org/W2110395205","https://openalex.org/W2141252802","https://openalex.org/W2145124910","https://openalex.org/W2156668683","https://openalex.org/W2167514198","https://openalex.org/W2170718640","https://openalex.org/W2179360174","https://openalex.org/W2489439822","https://openalex.org/W3144954235","https://openalex.org/W4255013851","https://openalex.org/W6676027986","https://openalex.org/W6684586841"],"related_works":["https://openalex.org/W2054139911","https://openalex.org/W1577524679","https://openalex.org/W2162027152","https://openalex.org/W4230869547","https://openalex.org/W2489439822","https://openalex.org/W2116397085","https://openalex.org/W2535372975","https://openalex.org/W4237143391","https://openalex.org/W2017101954","https://openalex.org/W2537636062"],"abstract_inverted_index":{"In":[0,68],"spite":[1],"of":[2,11,99],"the":[3,7,26,41,54,79,87],"mature":[4],"cell":[5,13],"structure,":[6],"memory":[8,55,80,93],"controller":[9,56,81],"architecture":[10,57,76],"Multi-level":[12],"(MLC)":[14],"NAND":[15],"Flash":[16],"memories":[17],"is":[18,97],"evolving":[19],"fast":[20],"in":[21,53,78],"an":[22],"attempt":[23],"to":[24,33],"improve":[25],"uncorrected/miscorrected":[27],"bit":[28],"error":[29],"rate":[30],"(UBER)":[31],"and":[32,65,105],"provide":[34],"a":[35,60,90],"more":[36,91],"flexible":[37,92],"usage":[38],"model":[39],"where":[40],"performance-reliability":[42],"trade-off":[43,62],"point":[44],"can":[45],"be":[46],"adjusted":[47],"at":[48,86],"runtime.":[49],"However,":[50],"optimization":[51],"techniques":[52],"cannot":[58],"avoid":[59],"strict":[61],"between":[63,103],"UBER":[64],"read":[66],"throughput.":[67],"this":[69],"paper,":[70],"we":[71],"show":[72],"that":[73],"co-optimizing":[74],"ECC":[75],"configuration":[77],"with":[82],"program":[83],"algorithm":[84],"selection":[85],"technology":[88],"layer,":[89],"sub-system":[94],"arises,":[95],"which":[96],"capable":[98],"unprecedented":[100],"trade-offs":[101],"points":[102],"performance":[104],"reliability.":[106],"\u00a9":[107],"2012":[108],"EDAA.":[109]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-02-09T09:26:11.010843","created_date":"2025-10-10T00:00:00"}