{"id":"https://openalex.org/W4210611780","doi":"https://doi.org/10.1109/date.2012.6176609","title":"Memory-map selection for firm real-time SDRAM controllers","display_name":"Memory-map selection for firm real-time SDRAM controllers","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W4210611780","doi":"https://doi.org/10.1109/date.2012.6176609"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176609","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176609","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064606209","display_name":"Sebastiaan Goossens","orcid":"https://orcid.org/0000-0002-0910-4952"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Goossens","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091251229","display_name":"Tim W. D. M. Kouters","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"T. Kouters","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059634103","display_name":"Benny \u00c5kesson","orcid":"https://orcid.org/0000-0003-2949-2080"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"B. Akesson","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048502768","display_name":"Kees Goossens","orcid":"https://orcid.org/0000-0001-7536-4050"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"K. Goossens","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"828","last_page":"831"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8115509152412415},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7261078357696533},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6871596574783325},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.672215461730957},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6569310426712036},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.6466504335403442},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5199912190437317},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.49770715832710266},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.489641010761261},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4816664457321167},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4764542877674103},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.468432754278183},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4659622013568878},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.42921626567840576},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.40448492765426636},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.34592610597610474},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30822989344596863},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.21557724475860596},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19809868931770325},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12246277928352356}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8115509152412415},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7261078357696533},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6871596574783325},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.672215461730957},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6569310426712036},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.6466504335403442},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5199912190437317},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.49770715832710266},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.489641010761261},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4816664457321167},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4764542877674103},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.468432754278183},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4659622013568878},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.42921626567840576},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.40448492765426636},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.34592610597610474},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30822989344596863},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.21557724475860596},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19809868931770325},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12246277928352356},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/date.2012.6176609","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176609","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:publications/8b6d215f-c40f-4924-a437-f54ae419cdf0","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/8b6d215f-c40f-4924-a437-f54ae419cdf0","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Goossens, S L M, Kouters, T W D M, Akesson, K B & Goossens, K G W 2012, Memory-map selection for firm real-time SDRAM controllers. in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2011), 14-18 March 2011, Dresden, Germany. Institute of Electrical and Electronics Engineers, Piscataway, pp. 828-831, 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) , Grenoble, France, 14/03/11. https://doi.org/10.1109/DATE.2012.6176609","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:tue:oai:pure.tue.nl:publications/8b6d215f-c40f-4924-a437-f54ae419cdf0","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/8b6d215f-c40f-4924-a437-f54ae419cdf0","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2011), 14-18 March 2011, Dresden, Germany, 828 - 831","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2102800454","https://openalex.org/W2116826559","https://openalex.org/W2121769217","https://openalex.org/W2125247549","https://openalex.org/W2151950158","https://openalex.org/W2161264993","https://openalex.org/W2167195657","https://openalex.org/W2167402388","https://openalex.org/W2168771580","https://openalex.org/W3142340790","https://openalex.org/W4237972311"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2557931434","https://openalex.org/W4285245242","https://openalex.org/W2019238062","https://openalex.org/W2185658074","https://openalex.org/W4243618206","https://openalex.org/W4393076761","https://openalex.org/W2138825797","https://openalex.org/W1455439291","https://openalex.org/W1725472669"],"abstract_inverted_index":{"A":[0],"modern":[1],"real-time":[2,30,50,169],"embedded":[3],"system":[4,36],"must":[5,43],"support":[6],"multiple":[7,77],"concurrently":[8],"running":[9],"applications.":[10],"To":[11,32],"reduce":[12],"costs,":[13],"critical":[14],"SoC":[15],"components":[16],"like":[17],"SDRAM":[18,75],"memories":[19],"are":[20,56],"often":[21],"shared":[22],"between":[23],"applications":[24,55,78],"with":[25],"a":[26,119,143,148,152,165],"variety":[27],"of":[28,52,65,95,122,125,137,161,167],"firm":[29],"requirements.":[31],"guarantee":[33],"that":[34,47],"the":[35,40,49,66,96,103,111,156,168],"works":[37],"as":[38],"intended,":[39],"memory":[41,67,71,88,175],"controller":[42],"be":[44],"configured":[45],"such":[46],"all":[48,53,126],"requirements":[51,83,171],"sharing":[54],"satisfied.":[57],"The":[58,107],"attainable":[59],"worst-case":[60,133],"bandwidth,":[61,138],"latency,":[62],"and":[63,140,159,172],"power":[64,176],"depend":[68],"largely":[69],"on":[70],"map":[72],"configuration.":[73],"Sharing":[74],"amongst":[76],"is":[79,130],"challenging,":[80],"since":[81],"their":[82],"might":[84],"call":[85],"for":[86,132],"different":[87],"maps.":[89],"This":[90,128],"paper":[91],"presents":[92],"an":[93,173],"exploration":[94],"memory-map":[97,104,153],"design":[98],"space.":[99],"Two":[100],"contributions":[101],"improve":[102],"selection":[105],"procedure.":[106],"first":[108],"contribution":[109],"reduces":[110],"minimum":[112],"access":[113,157],"granularity":[114,158],"by":[115],"interleaving":[116],"requests":[117],"over":[118],"configurable":[120],"number":[121,160],"banks":[123],"instead":[124],"banks.":[127],"technique":[129],"beneficial":[131],"performance":[134],"in":[135],"terms":[136],"latency":[139],"power.":[141],"As":[142],"second":[144],"contribution,":[145],"we":[146],"present":[147],"methodology":[149],"to":[150],"derive":[151],"configuration,":[154],"i.e.":[155],"interleaved":[162],"banks,":[163],"from":[164],"specification":[166],"application":[170],"overall":[174],"budget.":[177]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}