{"id":"https://openalex.org/W3148393872","doi":"https://doi.org/10.1109/date.2012.6176570","title":"Fast isomorphism testing for a graph-based analog circuit synthesis framework","display_name":"Fast isomorphism testing for a graph-based analog circuit synthesis framework","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W3148393872","doi":"https://doi.org/10.1109/date.2012.6176570","mag":"3148393872"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176570","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176570","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017152441","display_name":"Markus Mei\u00dfner","orcid":"https://orcid.org/0000-0002-5630-587X"},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"M. Meissner","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany"],"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007908609","display_name":"Oliver Mitea","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"O. Mitea","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany"],"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054162722","display_name":"Linda Luy","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"L. Luy","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany"],"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038049766","display_name":"Lars Hedrich","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"L. Hedrich","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany"],"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5017152441"],"corresponding_institution_ids":["https://openalex.org/I114090438"],"apc_list":null,"apc_paid":null,"fwci":0.8702,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.75988383,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"757","last_page":"762"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6941593289375305},{"id":"https://openalex.org/keywords/graph-isomorphism","display_name":"Graph isomorphism","score":0.5823096632957458},{"id":"https://openalex.org/keywords/isomorphism","display_name":"Isomorphism (crystallography)","score":0.565079391002655},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.47529637813568115},{"id":"https://openalex.org/keywords/subgraph-isomorphism-problem","display_name":"Subgraph isomorphism problem","score":0.42385202646255493},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.376346230506897},{"id":"https://openalex.org/keywords/line-graph","display_name":"Line graph","score":0.09070533514022827}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6941593289375305},{"id":"https://openalex.org/C61665672","wikidata":"https://www.wikidata.org/wiki/Q303100","display_name":"Graph isomorphism","level":4,"score":0.5823096632957458},{"id":"https://openalex.org/C203436722","wikidata":"https://www.wikidata.org/wiki/Q902950","display_name":"Isomorphism (crystallography)","level":3,"score":0.565079391002655},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.47529637813568115},{"id":"https://openalex.org/C131992880","wikidata":"https://www.wikidata.org/wiki/Q2528185","display_name":"Subgraph isomorphism problem","level":3,"score":0.42385202646255493},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.376346230506897},{"id":"https://openalex.org/C203776342","wikidata":"https://www.wikidata.org/wiki/Q1378376","display_name":"Line graph","level":3,"score":0.09070533514022827},{"id":"https://openalex.org/C115624301","wikidata":"https://www.wikidata.org/wiki/Q895901","display_name":"Crystal structure","level":2,"score":0.0},{"id":"https://openalex.org/C8010536","wikidata":"https://www.wikidata.org/wiki/Q160398","display_name":"Crystallography","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2012.6176570","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176570","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1482551403","https://openalex.org/W84561889","https://openalex.org/W1258892498","https://openalex.org/W2954463587","https://openalex.org/W2018568077","https://openalex.org/W2393701947","https://openalex.org/W1856194915","https://openalex.org/W3080158623","https://openalex.org/W2183579781","https://openalex.org/W2046021036"],"abstract_inverted_index":{"This":[0],"contribution":[1],"presents":[2],"a":[3,24,38,46,55],"major":[4],"improvement":[5],"for":[6,54],"our":[7],"analog":[8],"synthesis":[9,22,72],"framework":[10,80],"with":[11],"an":[12,83],"explorative":[13],"characteristic.":[14],"The":[15,59],"presented":[16,60],"approach":[17],"in":[18,92],"principle":[19],"allows":[20],"the":[21,30,63,71,79],"of":[23,27,40,87],"wide":[25],"range":[26,86],"circuits,":[28],"without":[29],"limitation":[31],"to":[32,42,81],"specific":[33],"circuit":[34,51],"classes.":[35],"Defined":[36],"by":[37],"specification":[39],"up":[41],"15":[43],"different":[44],"performances,":[45],"fully":[47],"sized,":[48],"transistor":[49],"level":[50],"is":[52],"synthesized":[53,88],"provided":[56],"process":[57],"technology.":[58],"work":[61],"reduces":[62,70],"needed":[64],"computational":[65],"effort":[66],"and":[67],"thus":[68],"drastically":[69],"time,":[73],"while":[74],"adding":[75],"new":[76],"abstraction":[77],"into":[78],"provide":[82],"even":[84],"wider":[85],"circuits":[89],"-":[90],"demonstrated":[91],"experimental":[93],"results.":[94]},"counts_by_year":[{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}