{"id":"https://openalex.org/W3152076439","doi":"https://doi.org/10.1109/date.2012.6176531","title":"A scan pattern debugger for partial scan industrial designs","display_name":"A scan pattern debugger for partial scan industrial designs","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W3152076439","doi":"https://doi.org/10.1109/date.2012.6176531","mag":"3152076439"},"language":"en","primary_location":{"id":"doi:10.1109/date.2012.6176531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176531","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064923800","display_name":"Kameshwar Chandrasekar","orcid":"https://orcid.org/0000-0002-6249-5593"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. Chandrasekar","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114006625","display_name":"Satyajayant Misra","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. K. Misra","raw_affiliation_strings":["ECE Department, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085174241","display_name":"Sharmila Sengupta","orcid":"https://orcid.org/0000-0003-1126-1049"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Sengupta","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. S. Hsiao","raw_affiliation_strings":["ECE Department, Virginia Tech, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5064923800"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34804197,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"558","last_page":"561"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9847999811172485,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugger","display_name":"Debugger","score":0.89223313331604},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8414881229400635},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7371115684509277},{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.7027075886726379},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.584978461265564},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4501599073410034},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4499243497848511},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4481401741504669},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41750919818878174},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3710249066352844},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3451770544052124},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22400623559951782},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1564830243587494},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.15605702996253967},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.11144277453422546}],"concepts":[{"id":"https://openalex.org/C2778485113","wikidata":"https://www.wikidata.org/wiki/Q193231","display_name":"Debugger","level":3,"score":0.89223313331604},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8414881229400635},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7371115684509277},{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.7027075886726379},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.584978461265564},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4501599073410034},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4499243497848511},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4481401741504669},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41750919818878174},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3710249066352844},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3451770544052124},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22400623559951782},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1564830243587494},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.15605702996253967},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.11144277453422546},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2012.6176531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176531","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1495288325","https://openalex.org/W2095962074","https://openalex.org/W2119241964","https://openalex.org/W2123485575","https://openalex.org/W2126851966","https://openalex.org/W2158212325","https://openalex.org/W2171012943","https://openalex.org/W3147914313","https://openalex.org/W3161197326"],"related_works":["https://openalex.org/W2143881398","https://openalex.org/W2118952760","https://openalex.org/W2075356617","https://openalex.org/W1974621628","https://openalex.org/W2274367941","https://openalex.org/W2390529848","https://openalex.org/W2763030692","https://openalex.org/W2092894550","https://openalex.org/W2073042086","https://openalex.org/W2789883751"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"an":[5,62],"implication":[6],"graph":[7],"based":[8],"sequential":[9],"logic":[10,30,74],"simulator":[11,75],"for":[12,55,93],"debugging":[13],"scan":[14,35,69,90],"pattern":[15,70,106],"failures":[16,107],"encountered":[17],"during":[18,29],"First":[19,103],"Silicon.":[20],"A":[21],"novel":[22],"Debug":[23,65],"Implication":[24],"Graph":[25],"(DIG)":[26],"is":[27,48],"constructed":[28],"simulation":[31],"of":[32,118],"the":[33,46,52,56,73,81,85,89,102],"failing":[34,57],"pattern.":[36],"An":[37],"efficient":[38],"node":[39],"traversal":[40],"mechanism":[41],"across":[42],"time":[43],"frames,":[44],"in":[45],"DIG,":[47],"used":[49],"to":[50,76,100],"perform":[51],"root-cause":[53,80],"analysis":[54],"scan-cells.":[58],"We":[59,83,97],"have":[60,112],"developed":[61],"Interactive":[63],"Pattern":[64],"environment":[66],"(IDE),":[67],"viz.":[68],"debugger,":[71],"around":[72],"systematically":[77],"analyze":[78],"and":[79],"failures.":[82],"integrated":[84],"proposed":[86],"technique":[87],"into":[88],"ATPG":[91],"flow":[92],"industrial":[94],"microprocessor":[95],"designs.":[96],"were":[98],"able":[99],"resolve":[101],"Silicon":[104],"logical":[105],"within":[108],"hours,":[109],"which":[110],"would":[111],"otherwise":[113],"taken":[114],"a":[115],"few":[116],"days":[117],"manual":[119],"effort.":[120]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}