{"id":"https://openalex.org/W2124786677","doi":"https://doi.org/10.1109/date.2011.5763290","title":"Architectural exploration of 3D FPGAs towards a better balance between area and delay","display_name":"Architectural exploration of 3D FPGAs towards a better balance between area and delay","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2124786677","doi":"https://doi.org/10.1109/date.2011.5763290","mag":"2124786677"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043130123","display_name":"Chia-I Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-I Chen","raw_affiliation_strings":["Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058246753","display_name":"B. Lee","orcid":"https://orcid.org/0009-0005-5512-0805"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bau-Cheng Lee","raw_affiliation_strings":["Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107969989","display_name":"Juinn-Dar Huang","orcid":"https://orcid.org/0000-0001-5961-7863"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Juinn-Dar Huang","raw_affiliation_strings":["Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":3.1325,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.92165453,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7158990502357483},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6968108415603638},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.6794905662536621},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.4887199401855469},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.46923381090164185},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4199097454547882},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3899979591369629}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7158990502357483},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6968108415603638},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.6794905662536621},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.4887199401855469},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.46923381090164185},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4199097454547882},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3899979591369629},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2023264348","https://openalex.org/W2045617353","https://openalex.org/W2139109474","https://openalex.org/W2170034300"],"related_works":["https://openalex.org/W2362198170","https://openalex.org/W2002703587","https://openalex.org/W3217667592","https://openalex.org/W2348798839","https://openalex.org/W2347214435","https://openalex.org/W2980006224","https://openalex.org/W2063534976","https://openalex.org/W2284838239","https://openalex.org/W2386436108","https://openalex.org/W2362584971"],"abstract_inverted_index":{"The":[0],"emerging":[1],"3D":[2,42,53,66,101,113,146],"technology,":[3],"which":[4,149],"stacks":[5],"multiple":[6],"dies":[7],"within":[8],"a":[9,22,33,41,108,132],"single":[10],"chip":[11],"and":[12,29,76,97,120,137],"utilizes":[13],"through-silicon":[14],"vias":[15],"(TSVs)":[16],"as":[17],"vertical":[18,70],"connections,":[19],"is":[20,72,80],"considered":[21],"promising":[23],"solution":[24],"for":[25,144],"achieving":[26],"better":[27,133],"performance":[28],"easy":[30],"integration.":[31],"Similarly,":[32],"generic":[34,145],"2D":[35,51,61],"FPGA":[36,147],"architecture":[37],"can":[38,150],"evolve":[39],"into":[40],"one":[43],"by":[44,54,65,92],"extending":[45],"its":[46],"signal":[47],"switching":[48],"scheme":[49],"from":[50],"to":[52,82,124,153],"means":[55],"of":[56,100,112],"TSVs.":[57],"However,":[58],"replacing":[59],"all":[60],"switch":[62],"boxes":[63],"(SBs)":[64],"ones":[67,130],"with":[68,87,131,156],"full":[69],"connectivity":[71],"found":[73],"both":[74],"area-consuming":[75],"resource-squandering.":[77],"Therefore,":[78],"it":[79],"possible":[81],"greatly":[83],"reduce":[84],"the":[85,95,127],"footprint":[86],"only":[88],"minor":[89],"delay":[90,159],"increase":[91],"properly":[93],"tailoring":[94],"structure":[96],"deployment":[98],"strategy":[99],"SB.":[102],"In":[103],"this":[104],"paper,":[105],"we":[106,140],"perform":[107],"comprehensive":[109],"architectural":[110,116],"exploration":[111],"FPGAs.":[114],"Various":[115],"alternatives":[117],"are":[118],"proposed":[119],"then":[121],"evaluated":[122],"thoroughly":[123],"pick":[125],"out":[126],"most":[128],"appropriate":[129],"balance":[134],"between":[135],"area":[136,155],"delay.":[138],"Finally,":[139],"recommend":[141],"several":[142],"configurations":[143],"architectures,":[148],"save":[151],"up":[152],"52%":[154],"virtually":[157],"no":[158],"penalty.":[160]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}