{"id":"https://openalex.org/W2087347065","doi":"https://doi.org/10.1109/date.2011.5763277","title":"ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications","display_name":"ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2087347065","doi":"https://doi.org/10.1109/date.2011.5763277","mag":"2087347065"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763277","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110517906","display_name":"Mojtaba Ebrahimi","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M Ebrahimi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065918596","display_name":"Seyed Ghassem Miremadi","orcid":"https://orcid.org/0000-0003-4347-4380"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S G Miremadi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054507740","display_name":"Hossein Asadi","orcid":"https://orcid.org/0000-0002-2721-8216"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"H Asadi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I133529467"],"apc_list":null,"apc_paid":null,"fwci":1.5201,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.81801638,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"66","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.7762385606765747},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6654651165008545},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5752490162849426},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5751984119415283},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.5695396065711975},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5494994521141052},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5206698179244995},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.4935845136642456},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4653322100639343},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.45593565702438354},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.43230023980140686},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.4252597689628601},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4180167317390442},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.41476643085479736},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4073840379714966},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3414574861526489},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30774205923080444},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.27677053213119507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2465018332004547},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.23183801770210266},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20238542556762695},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.20167526602745056},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1850610077381134},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.16105759143829346},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11323308944702148}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.7762385606765747},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6654651165008545},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5752490162849426},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5751984119415283},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.5695396065711975},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5494994521141052},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5206698179244995},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.4935845136642456},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4653322100639343},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.45593565702438354},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.43230023980140686},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.4252597689628601},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4180167317390442},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.41476643085479736},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4073840379714966},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3414574861526489},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30774205923080444},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.27677053213119507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2465018332004547},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.23183801770210266},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20238542556762695},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.20167526602745056},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1850610077381134},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.16105759143829346},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11323308944702148},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/date.2011.5763277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763277","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.725.2396","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.725.2396","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cdnc.itec.kit.edu/downloads/Papers/Ebrahimi11DATE.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.956.8346","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.956.8346","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://www.researchgate.net/profile/Mojtaba_Ebrahimi5/publication/224235988_ScTMR_A_scan_chain-based_error_recovery_technique_for_TMR_systems_in_safety-critical_applications/links/0deec529771ea2b26b000000.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W1849928240","https://openalex.org/W2110878481","https://openalex.org/W2112616228","https://openalex.org/W2115753002","https://openalex.org/W2119747227","https://openalex.org/W2126082910","https://openalex.org/W2134309495","https://openalex.org/W2149581858","https://openalex.org/W2151948111","https://openalex.org/W2377859122","https://openalex.org/W4232751114"],"related_works":["https://openalex.org/W2622269177","https://openalex.org/W1523508240","https://openalex.org/W2044069930","https://openalex.org/W2102538861","https://openalex.org/W2765347974","https://openalex.org/W2122334461","https://openalex.org/W2078707653","https://openalex.org/W2165400042","https://openalex.org/W4211237868","https://openalex.org/W1553526993"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,36,54,63,75,120],"roll-forward":[3],"error":[4,104],"recovery":[5,107],"technique":[6,84],"based":[7],"on":[8,85],"multiple":[9],"scan":[10,23],"chains":[11],"for":[12,27,90],"TMR":[13,18,37],"systems,":[14],"called":[15],"Scan":[16],"chained":[17],"(ScTMR).":[19],"ScTMR":[20,50,83],"reuses":[21],"the":[22,32,40,48,59,68,71,81,99,103],"chain":[24],"flip-flops":[25],"employed":[26],"testability":[28],"purposes":[29],"to":[30,57,66,70,113,128],"restore":[31,67],"correct":[33],"state":[34],"of":[35,42,109],"system":[38,69],"in":[39],"presence":[41],"transient":[43],"or":[44],"permanent":[45],"errors.":[46],"In":[47],"proposed":[49,82,100],"technique,":[51],"we":[52,78],"present":[53],"voter":[55],"circuitry":[56,65],"locate":[58],"faulty":[60],"module":[61],"and":[62,106,123],"controller":[64],"fault-free":[72],"state.":[73],"As":[74],"case":[76],"study,":[77],"have":[79],"implemented":[80],"an":[86],"embedded":[87],"processor,":[88],"suited":[89],"safety-critical":[91],"applications.":[92],"Exhaustive":[93],"fault":[94],"injection":[95],"experiments":[96],"reveal":[97],"that":[98],"architecture":[101],"has":[102],"detection":[105],"coverage":[108],"100%":[110],"with":[111],"respect":[112],"Single":[114],"Event":[115],"Upset":[116],"(SEU)":[117],"while":[118],"imposing":[119],"negligible":[121],"area":[122],"performance":[124],"overhead":[125],"as":[126],"compared":[127],"traditional":[129],"TMR-based":[130],"techniques.":[131]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
