{"id":"https://openalex.org/W2117703006","doi":"https://doi.org/10.1109/date.2011.5763227","title":"Abstract state machines as an intermediate representation for high-level synthesis","display_name":"Abstract state machines as an intermediate representation for high-level synthesis","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2117703006","doi":"https://doi.org/10.1109/date.2011.5763227","mag":"2117703006"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103181085","display_name":"Rohit Sinha","orcid":"https://orcid.org/0000-0001-9107-0239"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R Sinha","raw_affiliation_strings":["Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada","[Electrical and Computer Engineering University of Waterloo, Waterloo, CANADA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Electrical and Computer Engineering University of Waterloo, Waterloo, CANADA]","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074065388","display_name":"Hiren Patel","orcid":"https://orcid.org/0000-0003-2750-4471"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"H D Patel","raw_affiliation_strings":["Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada","[Electrical and Computer Engineering University of Waterloo, Waterloo, CANADA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Electrical and Computer Engineering University of Waterloo, Waterloo, CANADA]","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"77","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.808204710483551},{"id":"https://openalex.org/keywords/abstract-state-machines","display_name":"Abstract state machines","score":0.7731544971466064},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7455962896347046},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6880466938018799},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5904293656349182},{"id":"https://openalex.org/keywords/intermediate-language","display_name":"Intermediate language","score":0.5787332653999329},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5457505583763123},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5085781812667847},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.504986584186554},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.46721023321151733},{"id":"https://openalex.org/keywords/formalism","display_name":"Formalism (music)","score":0.4629330039024353},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.41163161396980286},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34559234976768494},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3404321074485779},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29647403955459595},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.25568583607673645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.808204710483551},{"id":"https://openalex.org/C145243422","wikidata":"https://www.wikidata.org/wiki/Q333385","display_name":"Abstract state machines","level":3,"score":0.7731544971466064},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7455962896347046},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6880466938018799},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5904293656349182},{"id":"https://openalex.org/C77660490","wikidata":"https://www.wikidata.org/wiki/Q244916","display_name":"Intermediate language","level":3,"score":0.5787332653999329},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5457505583763123},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5085781812667847},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.504986584186554},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.46721023321151733},{"id":"https://openalex.org/C73301696","wikidata":"https://www.wikidata.org/wiki/Q5469984","display_name":"Formalism (music)","level":3,"score":0.4629330039024353},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.41163161396980286},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34559234976768494},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3404321074485779},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29647403955459595},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.25568583607673645},{"id":"https://openalex.org/C558565934","wikidata":"https://www.wikidata.org/wiki/Q2743","display_name":"Musical","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2011.5763227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.914.7729","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.914.7729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecs.berkeley.edu/%7Ersinha/research/pubs/date2011.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1539438108","https://openalex.org/W1989435461","https://openalex.org/W2094998159","https://openalex.org/W2103581911","https://openalex.org/W2103798154","https://openalex.org/W2131023841","https://openalex.org/W2163437659","https://openalex.org/W2191327475","https://openalex.org/W6608987603"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2109177648"],"abstract_inverted_index":{"This":[0,119],"work":[1],"presents":[2],"a":[3,60,135],"high-level":[4],"synthesis":[5,123],"methodology":[6,131],"that":[7,106],"uses":[8],"the":[9,34,46,69,81,87,108,121,126],"abstract":[10],"state":[11],"machines":[12],"(ASMs)":[13],"formalism":[14],"as":[15,40],"an":[16,41,57,66,139,151],"intermediate":[17],"representation":[18],"(IR).":[19],"We":[20,32,128,142],"perform":[21],"scheduling":[22],"and":[23,28,51,72,138,146],"allocation":[24],"on":[25,65,150],"this":[26],"IR,":[27],"generate":[29],"synthesizable":[30],"VHDL.":[31],"have":[33],"following":[35],"advantages":[36],"when":[37],"using":[38,94],"ASMs":[39],"IR:":[42],"1)":[43],"it":[44,55,74],"allows":[45,80],"specification":[47],"of":[48,59,68,83,134],"both":[49],"sequential":[50,70],"parallel":[52],"computation,":[53],"2)":[54],"supports":[56],"extension":[58],"clean":[61],"timing":[62],"model":[63],"based":[64],"interpretation":[67],"semantics,":[71,78],"3)":[73],"has":[75],"well-defined":[76],"formal":[77,84],"which":[79],"integration":[82],"methods":[85],"into":[86,114],"methodology.":[88],"While":[89],"we":[90,96],"specify":[91],"our":[92,130,148],"designs":[93,145,149],"ASMs,":[95],"do":[97],"not":[98],"mandate":[99],"this.":[100],"Instead,":[101],"one":[102],"can":[103],"create":[104],"translators":[105],"convert":[107],"algorithmic":[109],"specifications":[110],"from":[111],"C-like":[112],"languages":[113],"their":[115],"equivalent":[116],"ASM":[117],"specifications.":[118],"makes":[120],"hardware":[122],"transparent":[124],"to":[125],"designer.":[127],"experiment":[129],"with":[132],"examples":[133],"FIR,":[136],"microprocessor,":[137],"edge":[140],"detector.":[141],"synthesize":[143],"these":[144],"validate":[147],"FPGA.":[152]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
