{"id":"https://openalex.org/W1981792495","doi":"https://doi.org/10.1109/date.2011.5763220","title":"An efficient algorithm for multi-domain clock skew scheduling","display_name":"An efficient algorithm for multi-domain clock skew scheduling","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W1981792495","doi":"https://doi.org/10.1109/date.2011.5763220","mag":"1981792495"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763220","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041392686","display_name":"Yanling Zhi","orcid":"https://orcid.org/0000-0002-4028-9289"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yanling Zhi","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109302065","display_name":"Wai-Shing Luk","orcid":"https://orcid.org/0009-0006-8322-8079"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wai-Shing Luk","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052779900","display_name":"Hai Zhou","orcid":"https://orcid.org/0000-0002-0869-3038"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["Department of EECS, Northwestern University, USA","State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"Department of EECS, Northwestern University, USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037328458","display_name":"Changhao Yan","orcid":"https://orcid.org/0000-0002-8936-3945"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Changhao Yan","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020841047","display_name":"Hengliang Zhu","orcid":"https://orcid.org/0000-0002-0338-9256"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hengliang Zhu","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100342928","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8711-753X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5041392686"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"],"apc_list":null,"apc_paid":null,"fwci":1.2593,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80194712,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7463924884796143},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6380059719085693},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5846415162086487},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5647251605987549},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5041631460189819},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47509586811065674},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.4441748261451721},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.44239819049835205},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.43796902894973755},{"id":"https://openalex.org/keywords/laptop","display_name":"Laptop","score":0.4352869987487793},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.41172516345977783},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3875330090522766},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.17580831050872803},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.17096439003944397},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16883042454719543}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7463924884796143},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6380059719085693},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5846415162086487},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5647251605987549},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5041631460189819},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47509586811065674},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.4441748261451721},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.44239819049835205},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.43796902894973755},{"id":"https://openalex.org/C2780008327","wikidata":"https://www.wikidata.org/wiki/Q3962","display_name":"Laptop","level":2,"score":0.4352869987487793},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.41172516345977783},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3875330090522766},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.17580831050872803},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17096439003944397},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16883042454719543},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763220","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1983093080","https://openalex.org/W2011778848","https://openalex.org/W2028145673","https://openalex.org/W2096283348","https://openalex.org/W2100525812","https://openalex.org/W2135347849","https://openalex.org/W2142785340","https://openalex.org/W2163318442","https://openalex.org/W2168129320","https://openalex.org/W3004540582","https://openalex.org/W3145128584","https://openalex.org/W4231706861","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4232019485","https://openalex.org/W2164834710","https://openalex.org/W2156857157","https://openalex.org/W2076413498","https://openalex.org/W2028052815","https://openalex.org/W2123512677","https://openalex.org/W4327499872","https://openalex.org/W2116259070","https://openalex.org/W2128528443","https://openalex.org/W2097706495"],"abstract_inverted_index":{"Conventional":[0],"clock":[1,48,54,69],"skew":[2,55],"scheduling":[3,56],"for":[4,50,122,134],"sequential":[5],"circuits":[6],"can":[7,19,75,107,115],"be":[8,20,76,108,116],"formulated":[9,77,109],"as":[10,26,78,110],"a":[11,42,79,111,130,142,194,197],"minimum":[12],"cycle":[13],"ratio":[14],"(MCR)":[15],"problem,":[16],"and":[17,161,183],"hence":[18],"solved":[21,117],"effectively":[22,118],"by":[23,63],"methods":[24],"such":[25],"Howard's":[27,132],"algorithm.":[28,165],"However,":[29],"its":[30],"application":[31],"is":[32,86],"practically":[33],"limited":[34],"due":[35],"to":[36,59,88,146],"the":[37,51,65,102,123,149,159,171,180,185],"difficulties":[38],"in":[39,91,179,188],"reliably":[40],"implementing":[41],"large":[43],"set":[44],"of":[45,68,163,170],"arbitrary":[46],"dedicated":[47],"delays":[49],"flip-flops.":[52],"Multi-domain":[53],"was":[57],"proposed":[58],"tackle":[60],"this":[61,73,94,136],"impracticality":[62],"constraining":[64],"total":[66],"number":[67],"delays.":[70],"Even":[71],"though":[72],"problem":[74,106,137],"mixed":[80],"integer":[81],"linear":[82],"programming":[83],"(MILP),":[84],"it":[85],"expensive":[87],"solve":[89],"optimally":[90],"general.":[92],"In":[93,126],"paper,":[95],"we":[96,128],"show":[97,157],"that,":[98],"under":[99],"mild":[100],"restrictions,":[101],"underlying":[103],"domain":[104],"assignment":[105],"special":[112],"MILP":[113],"that":[114],"using":[119],"similar":[120],"techniques":[121],"MCR":[124],"problem.":[125],"particular,":[127],"design":[129],"generalized":[131],"algorithm":[133,145],"solving":[135],"efficiently.":[138],"We":[139],"also":[140],"develop":[141],"critical-cycle-oriented":[143],"refinement":[144],"further":[147],"improve":[148],"results.":[150],"The":[151],"experimental":[152],"results":[153],"on":[154,193],"ISCAS89":[155],"benchmarks":[156],"both":[158],"accuracy":[160],"efficiency":[162],"our":[164],"For":[166],"example,":[167],"only":[168],"4.3%":[169],"tests":[172,186],"have":[173],"larger":[174],"than":[175,190],"1%":[176],"degradation":[177],"(3%":[178],"worst":[181],"case),":[182],"all":[184],"finish":[187],"less":[189],"0.7":[191],"seconds":[192],"laptop":[195],"with":[196],"2.1GHz":[198],"processor.":[199]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
