{"id":"https://openalex.org/W2139315799","doi":"https://doi.org/10.1109/date.2011.5763180","title":"A high-level analytical model for application specific CMP design exploration","display_name":"A high-level analytical model for application specific CMP design exploration","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2139315799","doi":"https://doi.org/10.1109/date.2011.5763180","mag":"2139315799"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763180","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009555410","display_name":"Aaron Cassidy","orcid":"https://orcid.org/0000-0002-0431-2496"},"institutions":[{"id":"https://openalex.org/I145311948","display_name":"Johns Hopkins University","ror":"https://ror.org/00za53h95","country_code":"US","type":"education","lineage":["https://openalex.org/I145311948"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A Cassidy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","institution_ids":["https://openalex.org/I145311948"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218","institution_ids":["https://openalex.org/I145311948"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032611571","display_name":"Kai Yu","orcid":"https://orcid.org/0000-0002-4778-4389"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai Yu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA-15213"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA-15213","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025364065","display_name":"Haolang Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I145311948","display_name":"Johns Hopkins University","ror":"https://ror.org/00za53h95","country_code":"US","type":"education","lineage":["https://openalex.org/I145311948"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Haolang Zhou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","institution_ids":["https://openalex.org/I145311948"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218","institution_ids":["https://openalex.org/I145311948"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057789499","display_name":"Andreas G. Andreou","orcid":"https://orcid.org/0000-0003-3826-600X"},"institutions":[{"id":"https://openalex.org/I145311948","display_name":"Johns Hopkins University","ror":"https://ror.org/00za53h95","country_code":"US","type":"education","lineage":["https://openalex.org/I145311948"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A G Andreou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA","institution_ids":["https://openalex.org/I145311948"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218","institution_ids":["https://openalex.org/I145311948"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3301,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.80127389,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8375445604324341},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6940641403198242},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6701853275299072},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.6675772070884705},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6148859858512878},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5826111435890198},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5135889053344727},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4837953746318817},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.483265221118927},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47797319293022156},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4434175491333008},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41875195503234863},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36201801896095276},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34276315569877625},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1013379693031311}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8375445604324341},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6940641403198242},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6701853275299072},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.6675772070884705},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6148859858512878},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5826111435890198},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5135889053344727},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4837953746318817},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.483265221118927},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47797319293022156},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4434175491333008},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41875195503234863},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36201801896095276},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34276315569877625},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1013379693031311},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763180","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W143540806","https://openalex.org/W1976599907","https://openalex.org/W2022038016","https://openalex.org/W2035720033","https://openalex.org/W2041653803","https://openalex.org/W2079726719","https://openalex.org/W2079942837","https://openalex.org/W2099714261","https://openalex.org/W2104225326","https://openalex.org/W2108434244","https://openalex.org/W2115676933","https://openalex.org/W2120368896","https://openalex.org/W2152530926","https://openalex.org/W2154962115","https://openalex.org/W2155396321","https://openalex.org/W2399061103","https://openalex.org/W3150149233","https://openalex.org/W4205555264","https://openalex.org/W4255841148","https://openalex.org/W6712446660"],"related_works":["https://openalex.org/W4386869637","https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W3146054601","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4313484792","https://openalex.org/W4387251174","https://openalex.org/W2169880332","https://openalex.org/W4281784598"],"abstract_inverted_index":{"We":[0],"present":[1,49],"a":[2,29,37],"high-level":[3,57],"analytical":[4,23],"model":[5,24,41],"for":[6,32,39,53,72],"chip-multiprocessors":[7],"(CMPs)":[8],"that":[9,76],"encompasses":[10],"processors,":[11],"memory,":[12],"and":[13,90,99],"communication":[14],"in":[15],"an":[16,50],"area-constrained,":[17],"global":[18],"optimization":[19],"process.":[20],"Applying":[21],"this":[22],"to":[25,44,65],"the":[26,55,63,67,83,94],"design":[27,45],"of":[28,69,97],"symmetric":[30],"CMP":[31,58],"speech":[33],"recognition,":[34],"we":[35,48],"demonstrate":[36],"methodology":[38],"estimating":[40],"parameters":[42],"prior":[43],"exploration.":[46],"Then":[47],"automated":[51],"approach":[52],"finding":[54],"optimal":[56],"architecture.":[59],"The":[60],"result":[61],"is":[62],"ability":[64],"find":[66],"allocation":[68],"silicon":[70],"resources":[71],"each":[73],"architectural":[74],"element":[75],"maximizes":[77],"overall":[78],"system":[79],"performance.":[80],"This":[81],"balances":[82],"performance":[84],"gains":[85],"from":[86],"parallelism,":[87],"processor":[88],"microarchitecture,":[89],"cache":[91],"memory":[92],"with":[93],"energy-delay":[95],"costs":[96],"computation":[98],"communication.":[100]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}