{"id":"https://openalex.org/W2168308580","doi":"https://doi.org/10.1109/date.2011.5763144","title":"Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools","display_name":"Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2168308580","doi":"https://doi.org/10.1109/date.2011.5763144","mag":"2168308580"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011464762","display_name":"Kees Vissers","orcid":"https://orcid.org/0000-0002-6249-315X"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K Vissers","raw_affiliation_strings":["Xilinx, Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014827775","display_name":"Stephen Neuendorffer","orcid":"https://orcid.org/0000-0003-2956-8428"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S Neuendorffer","raw_affiliation_strings":["Xilinx, Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036634922","display_name":"Jos\u00e9 M. Noguera","orcid":"https://orcid.org/0000-0001-8181-0934"},"institutions":[{"id":"https://openalex.org/I4210101362","display_name":"Xilinx (Ireland)","ror":"https://ror.org/00pahkj72","country_code":"IE","type":"company","lineage":["https://openalex.org/I32923980","https://openalex.org/I4210101362"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"J Noguera","raw_affiliation_strings":["Xilinx, Inc., Dublin, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., Dublin, Ireland","institution_ids":["https://openalex.org/I4210101362"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7601,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.7055505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7586044073104858},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7457605600357056},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6545888185501099},{"id":"https://openalex.org/keywords/high-definition-television","display_name":"High-definition television","score":0.6017528772354126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5684102177619934},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5634070634841919},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.520386815071106},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34566396474838257}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7586044073104858},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7457605600357056},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6545888185501099},{"id":"https://openalex.org/C2778129506","wikidata":"https://www.wikidata.org/wiki/Q133454","display_name":"High-definition television","level":2,"score":0.6017528772354126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5684102177619934},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5634070634841919},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.520386815071106},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34566396474838257},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2091636254","https://openalex.org/W2166029537"],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W2139708877","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2160632767","https://openalex.org/W1608572506","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W2000188956","https://openalex.org/W1973862904"],"abstract_inverted_index":{"Modern":[0],"FPGAs":[1],"enable":[2],"complete":[3],"system":[4],"designs":[5],"that":[6,19],"include":[7],"processors,":[8],"interconnect":[9],"systems,":[10],"memory":[11],"subsystems":[12],"and":[13],"a":[14],"number":[15],"of":[16],"application":[17],"functions":[18],"are":[20],"implemented":[21],"using":[22],"High-Level":[23],"Synthesis":[24],"tools.":[25]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
