{"id":"https://openalex.org/W2126997714","doi":"https://doi.org/10.1109/date.2011.5763102","title":"Timing-constrained I/O buffer placement for flip-chip designs","display_name":"Timing-constrained I/O buffer placement for flip-chip designs","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2126997714","doi":"https://doi.org/10.1109/date.2011.5763102","mag":"2126997714"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763102","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5107854763","display_name":"Zhiwei Chen","orcid":"https://orcid.org/0009-0000-5960-5731"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Zhi-Wei Chen","raw_affiliation_strings":["College of Engineering, Chung Hua University, Hsinchu, Taiwan","College of Engineering Chung-Hua University, Hsinchu, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering, Chung Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"College of Engineering Chung-Hua University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I59460038"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071940138","display_name":"Jin-Tai Yan","orcid":"https://orcid.org/0000-0002-7614-2545"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Tai Yan","raw_affiliation_strings":["Department of Computer Science and Information Engineering, Chung Hua University, Hsinchu, Taiwan","Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R. O. C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, Chung Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R. O. C","institution_ids":["https://openalex.org/I59460038"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I59460038"],"apc_list":null,"apc_paid":null,"fwci":0.4475,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.60930352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6312041282653809},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.6132130026817322},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.562247633934021},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.5280340909957886},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5089380741119385},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4348887503147125},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.4348568916320801},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40936675667762756},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3780800700187683},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33765897154808044},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3282829225063324},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.322133332490921},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.2931680679321289},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21799752116203308},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.19407767057418823},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19137313961982727}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6312041282653809},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.6132130026817322},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.562247633934021},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.5280340909957886},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5089380741119385},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4348887503147125},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.4348568916320801},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40936675667762756},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3780800700187683},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33765897154808044},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3282829225063324},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.322133332490921},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2931680679321289},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21799752116203308},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.19407767057418823},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19137313961982727},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763102","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W180909918","https://openalex.org/W1841949876","https://openalex.org/W1969208860","https://openalex.org/W2075265327","https://openalex.org/W2090146793","https://openalex.org/W2098488748","https://openalex.org/W2098851424","https://openalex.org/W2102502584","https://openalex.org/W2109786540","https://openalex.org/W2141835763","https://openalex.org/W2151190382","https://openalex.org/W4210521336","https://openalex.org/W4237664122","https://openalex.org/W6642678704","https://openalex.org/W6676547695"],"related_works":["https://openalex.org/W1974474301","https://openalex.org/W2135304146","https://openalex.org/W4231811236","https://openalex.org/W4386523879","https://openalex.org/W4293024026","https://openalex.org/W1970795504","https://openalex.org/W4327810905","https://openalex.org/W2138208643","https://openalex.org/W3205346928","https://openalex.org/W2094806828"],"abstract_inverted_index":{"Due":[0],"to":[1,53],"inappropriate":[2],"assignment":[3],"of":[4,10,16,33,70,88,93],"bump":[5,65],"pads":[6,66],"or":[7],"improper":[8],"placement":[9,37],"I/O":[11,17,35,55,62],"buffers,":[12],"the":[13,22,31,68,71,94,102,105,117],"configured":[14],"delays":[15],"signals":[18],"may":[19],"not":[20],"satisfy":[21],"timing":[23,72,81,107],"requirement":[24],"inside":[25],"die":[26],"core.":[27],"In":[28],"this":[29],"paper,":[30],"problem":[32],"timing-constrained":[34,113],"buffer":[36,59],"in":[38],"an":[39,47],"area-IO":[40],"flip-chip":[41],"design":[42],"is":[43,51],"firstly":[44],"formulated.":[45],"Furthermore,":[46],"efficient":[48],"two-phase":[49],"approach":[50,84],"proposed":[52],"place":[54],"buffers":[56],"onto":[57],"feasible":[58],"locations":[60],"between":[61],"pins":[63],"and":[64,91],"with":[67,75,79],"consideration":[69],"constraints.":[73],"Compared":[74],"Peng's":[76],"SA-based":[77,118],"approach,":[78],"no":[80],"constraint,":[82],"our":[83,109],"can":[85],"reduce":[86],"71.82%":[87],"total":[89],"wirelength":[90],"55.74%":[92],"maximum":[95],"delay":[96],"for":[97],"7":[98],"tested":[99],"cases":[100],"on":[101],"average.":[103],"Under":[104],"given":[106],"constraints,":[108],"result":[110],"obtains":[111],"higher":[112],"satisfaction":[114],"ratio(TCSR)":[115],"than":[116],"approach.":[119]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
