{"id":"https://openalex.org/W2148034879","doi":"https://doi.org/10.1109/date.2011.5763089","title":"Power management verification experiences in Wireless SoCs","display_name":"Power management verification experiences in Wireless SoCs","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2148034879","doi":"https://doi.org/10.1109/date.2011.5763089","mag":"2148034879"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016213907","display_name":"Bhanu Kapoor","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B Kapoor","raw_affiliation_strings":["Mimasic, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mimasic, Richardson, TX, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042449261","display_name":"Andrew Hunter","orcid":"https://orcid.org/0000-0003-3786-4008"},"institutions":[{"id":"https://openalex.org/I4210156213","display_name":"American Rock Mechanics Association","ror":"https://ror.org/05vfrxy92","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I4210156213"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A Hunter","raw_affiliation_strings":["ARM, Inc., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARM, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210156213"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101699786","display_name":"Prabhakar Tiwari","orcid":"https://orcid.org/0000-0003-3923-9126"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P Tiwari","raw_affiliation_strings":["Synopsys, Inc., Chandler, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Chandler, AZ, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.2475356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.666109561920166},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.6514018774032593},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6225422620773315},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6083877682685852},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6082996129989624},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5693759322166443},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5253906846046448},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5158733129501343},{"id":"https://openalex.org/keywords/power-domains","display_name":"Power domains","score":0.48792120814323425},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.4584590494632721},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.4488263726234436},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.43886715173721313},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4291917383670807},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34306466579437256},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34216657280921936},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28381475806236267},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.14096710085868835},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13419264554977417},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.10798525810241699},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.10391196608543396},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.08044975996017456},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.0775299072265625}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.666109561920166},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.6514018774032593},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6225422620773315},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6083877682685852},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6082996129989624},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5693759322166443},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5253906846046448},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5158733129501343},{"id":"https://openalex.org/C16021271","wikidata":"https://www.wikidata.org/wiki/Q17152552","display_name":"Power domains","level":3,"score":0.48792120814323425},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.4584590494632721},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.4488263726234436},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.43886715173721313},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4291917383670807},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34306466579437256},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34216657280921936},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28381475806236267},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.14096710085868835},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13419264554977417},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.10798525810241699},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.10391196608543396},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.08044975996017456},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0775299072265625},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation &amp; Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1976634368"],"related_works":["https://openalex.org/W2546524276","https://openalex.org/W4226239708","https://openalex.org/W2152979262","https://openalex.org/W2145376025","https://openalex.org/W2020434689","https://openalex.org/W2138778793","https://openalex.org/W1949070338","https://openalex.org/W2103368706","https://openalex.org/W2358819000","https://openalex.org/W1999768152"],"abstract_inverted_index":{"We":[0,35],"look":[1],"into":[2,70],"the":[3,25,38,44,68,87],"validation":[4],"a":[5],"power":[6,33,51,72],"managed":[7],"ARM":[8],"Cortex":[9],"A-8":[10],"core":[11,46],"used":[12,23],"in":[13,42,80],"SoCs":[14],"targeted":[15],"for":[16],"mobile":[17],"segment.":[18],"Low":[19],"Power":[20],"design":[21],"techniques":[22],"on":[24,37],"chip":[26,79],"include":[27],"clock":[28],"gating,":[29],"voltage":[30,59],"scaling,":[31],"and":[32,54,74],"gating.":[34],"focus":[36],"verification":[39],"challenges":[40],"faced":[41],"designing":[43],"processor":[45],"including":[47],"RTL":[48],"modeling":[49],"of":[50,58,62,78],"switches,":[52],"isolation,":[53],"level-shifting":[55],"cells,":[56],"simulation":[57],"ramps,":[60],"generation":[61],"appropriate":[63],"control":[64],"signals":[65],"to":[66],"put":[67],"device":[69],"various":[71],"states,":[73],"ensuring":[75],"correct":[76],"operation":[77],"these":[81,90],"states":[82],"as":[83,85],"well":[84],"during":[86],"transitions":[88],"between":[89],"states.":[91]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
