{"id":"https://openalex.org/W2132481498","doi":"https://doi.org/10.1109/date.2011.5763060","title":"Cycle-count-accurate processor modeling for fast and accurate system-level simulation","display_name":"Cycle-count-accurate processor modeling for fast and accurate system-level simulation","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2132481498","doi":"https://doi.org/10.1109/date.2011.5763060","mag":"2132481498"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066083714","display_name":"Chen-Kang Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Kang Lo","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103885559","display_name":"Li-Chun Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Li-Chun Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010956144","display_name":"Meng-Huan Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Meng-Huan Wu","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046952008","display_name":"Ren\u2010Song Tsay","orcid":"https://orcid.org/0000-0002-8997-0219"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ren-Song Tsay","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":1.3301,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.79945405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7957614660263062},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6506762504577637},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.6001311540603638},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.5650312900543213},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5314546823501587},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47861164808273315},{"id":"https://openalex.org/keywords/cycle-count","display_name":"Cycle count","score":0.4719369113445282},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4625261425971985},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4347715675830841},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.41943150758743286},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.41691792011260986},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.41460901498794556},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36016416549682617},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.3429182767868042},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21036013960838318},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.2081259787082672},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19842690229415894},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.16989338397979736},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10674458742141724}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7957614660263062},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6506762504577637},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.6001311540603638},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.5650312900543213},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5314546823501587},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47861164808273315},{"id":"https://openalex.org/C94196362","wikidata":"https://www.wikidata.org/wiki/Q5198153","display_name":"Cycle count","level":2,"score":0.4719369113445282},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4625261425971985},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4347715675830841},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.41943150758743286},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.41691792011260986},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.41460901498794556},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36016416549682617},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.3429182767868042},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21036013960838318},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.2081259787082672},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19842690229415894},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.16989338397979736},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10674458742141724},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1567646530","https://openalex.org/W1973268332","https://openalex.org/W1981305988","https://openalex.org/W1982033096","https://openalex.org/W2016837603","https://openalex.org/W2082421967","https://openalex.org/W2096258337","https://openalex.org/W2099940607","https://openalex.org/W2102570774","https://openalex.org/W2113952960","https://openalex.org/W2118297067","https://openalex.org/W2129759021","https://openalex.org/W2139354295","https://openalex.org/W2143285457","https://openalex.org/W2166358385"],"related_works":["https://openalex.org/W2113901785","https://openalex.org/W4251804317","https://openalex.org/W2153228602","https://openalex.org/W2000267092","https://openalex.org/W2150776253","https://openalex.org/W2754873661","https://openalex.org/W124901208","https://openalex.org/W2138511884","https://openalex.org/W3011821879","https://openalex.org/W2539417988"],"abstract_inverted_index":{"Ideally,":[0],"system-level":[1],"simulation":[2,7,32,50],"should":[3],"provide":[4],"a":[5,62],"high":[6,49],"speed":[8],"with":[9,77],"sufficient":[10],"timing":[11,37,45,54,85],"details":[12,38],"for":[13],"both":[14],"functional":[15,87],"verification":[16],"and":[17,24,73,82,86],"performance":[18],"evaluation.":[19],"However,":[20],"existing":[21],"cycle-accurate":[22],"(CA)":[23],"cycle-approximate":[25],"(CX)":[26],"processor":[27,66,90],"models":[28,76],"either":[29],"incur":[30],"low":[31,40],"speeds":[33,51],"due":[34,42],"to":[35,43],"excessive":[36],"or":[39],"accuracy":[41,55],"simplified":[44],"models.":[46],"To":[47],"achieve":[48],"while":[52,109],"maintaining":[53],"of":[56],"the":[57,97,105,111,118],"system":[58],"simulation,":[59],"we":[60],"propose":[61],"first":[63],"cycle-count-accurate":[64],"(CCA)":[65],"modeling":[67],"approach":[68],"which":[69],"pre-abstracts":[70],"internal":[71],"pipeline":[72],"cache":[74],"into":[75],"accurate":[78,84],"cycle":[79,114],"count":[80,115],"information":[81,116],"guarantees":[83],"behaviors":[88],"on":[89],"interface.":[91],"The":[92],"experimental":[93],"results":[94],"show":[95],"that":[96],"CCA":[98],"model":[99,108],"performs":[100],"50":[101],"times":[102],"faster":[103],"than":[104],"corresponding":[106],"CA":[107],"providing":[110],"same":[112],"execution":[113],"as":[117],"target":[119],"RTL":[120],"model.":[121]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}