{"id":"https://openalex.org/W2154781197","doi":"https://doi.org/10.1109/date.2011.5763042","title":"A clock-gating based capture power droop reduction methodology for at-speed scan testing","display_name":"A clock-gating based capture power droop reduction methodology for at-speed scan testing","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2154781197","doi":"https://doi.org/10.1109/date.2011.5763042","mag":"2154781197"},"language":"en","primary_location":{"id":"doi:10.1109/date.2011.5763042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100453374","display_name":"Bo Yang","orcid":"https://orcid.org/0000-0003-1559-0202"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bo Yang","raw_affiliation_strings":["DFT Engineering, NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060188846","display_name":"Amit Sanghani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A Sanghani","raw_affiliation_strings":["DFT Engineering, NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102049491","display_name":"SK Sarangi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S Sarangi","raw_affiliation_strings":["AMD Corporation, Sunnyvale, CA, USA"],"affiliations":[{"raw_affiliation_string":"AMD Corporation, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103115781","display_name":"Chunsheng Liu","orcid":"https://orcid.org/0000-0002-3784-662X"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chunsheng Liu","raw_affiliation_strings":["Test Development, Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Test Development, Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100453374"],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":2.2668,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.89243104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.9318655729293823},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7232848405838013},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5781649351119995},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5460417866706848},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.44104188680648804},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43358302116394043},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.42835763096809387},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42411312460899353},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41056957840919495},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31054961681365967},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.21133798360824585},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19101816415786743},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.18852946162223816},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1836135983467102},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13336172699928284},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.07848331332206726}],"concepts":[{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.9318655729293823},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7232848405838013},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5781649351119995},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5460417866706848},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.44104188680648804},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43358302116394043},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42835763096809387},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42411312460899353},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41056957840919495},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31054961681365967},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.21133798360824585},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19101816415786743},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.18852946162223816},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1836135983467102},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13336172699928284},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.07848331332206726},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2011.5763042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2011.5763042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Design, Automation & Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2004822659","https://openalex.org/W2102355929","https://openalex.org/W2103252557","https://openalex.org/W2104677752","https://openalex.org/W2111531873","https://openalex.org/W2111569953","https://openalex.org/W2121200165","https://openalex.org/W2126152478","https://openalex.org/W2149280425","https://openalex.org/W2149998114","https://openalex.org/W2154421641","https://openalex.org/W2164374928","https://openalex.org/W3140239545"],"related_works":["https://openalex.org/W2523432015","https://openalex.org/W2765340260","https://openalex.org/W2153130273","https://openalex.org/W2076823813","https://openalex.org/W3008686614","https://openalex.org/W2143080380","https://openalex.org/W1589163333","https://openalex.org/W2060924671","https://openalex.org/W3180072344","https://openalex.org/W2075810349"],"abstract_inverted_index":{"Excessive":[0],"power":[1,31,49,60],"dissipation":[2],"caused":[3],"by":[4],"large":[5,19],"amount":[6],"of":[7,76,111],"switching":[8,23],"activities":[9,24],"has":[10],"been":[11],"a":[12,56,77],"major":[13],"issue":[14],"in":[15],"scan-based":[16],"testing.":[17],"For":[18],"designs,":[20],"the":[21,41,48,74,85],"excessive":[22],"during":[25,62],"launch":[26],"cycle":[27],"can":[28],"cause":[29],"severe":[30],"droop,":[32],"which":[33],"cannot":[34],"be":[35],"recovered":[36],"before":[37],"capture":[38,64],"cycle,":[39],"rendering":[40],"at-speed":[42,67],"scan":[43,63],"testing":[44],"more":[45],"susceptible":[46],"to":[47,58,83],"droop.":[50],"In":[51],"this":[52,112],"paper,":[53],"we":[54],"present":[55],"methodology":[57,89],"avoid":[59],"droop":[61],"without":[65],"compromising":[66],"test":[68],"coverage.":[69],"It":[70],"is":[71,90,100,106,114],"based":[72],"on":[73,116],"use":[75],"low":[78],"area":[79],"overhead":[80],"hardware":[81],"controller":[82],"control":[84],"clock":[86],"gates.":[87],"The":[88,109],"ATPG":[91],"(Automatic":[92],"Test":[93],"Pattern":[94],"Generation)-independent,":[95],"hence":[96],"pattern":[97,104],"generation":[98],"time":[99],"not":[101,107],"affected":[102],"and":[103],"manipulation":[105],"required.":[108],"effectiveness":[110],"technique":[113],"demonstrated":[115],"several":[117],"industrial":[118],"designs.":[119]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}