{"id":"https://openalex.org/W3149530953","doi":"https://doi.org/10.1109/date.2010.5457237","title":"MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture","display_name":"MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3149530953","doi":"https://doi.org/10.1109/date.2010.5457237","mag":"3149530953"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://porto.polito.it/2335729/1/published_02.4_4.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006172044","display_name":"Sergio V. Tota","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Sergio V Tota","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036528695","display_name":"Mario R. Casu","orcid":"https://orcid.org/0000-0002-1026-0178"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario R Casu","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045326285","display_name":"Massimo Ruo Roch","orcid":"https://orcid.org/0000-0001-7313-8017"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Ruo Roch","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086505292","display_name":"Luca Rostagno","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Rostagno","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077512098","display_name":"Maurizio Zamboni","orcid":"https://orcid.org/0000-0001-8179-5973"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maurizio Zamboni","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5006172044"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":2.849,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.91622199,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"45","last_page":"50"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8596477508544922},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.5998677015304565},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5984899997711182},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5738409757614136},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5548730492591858},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5324832797050476},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5184354782104492},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5089080333709717},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.49724557995796204},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4645763337612152},{"id":"https://openalex.org/keywords/semaphore","display_name":"Semaphore","score":0.457735538482666},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4493095874786377},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.44852912425994873},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.42880699038505554},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42443808913230896},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.37953874468803406},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.34906888008117676},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.32773953676223755},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.23462119698524475},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.1853095293045044},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1808655560016632},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1393280327320099},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11095863580703735},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.09919556975364685}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8596477508544922},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.5998677015304565},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5984899997711182},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5738409757614136},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5548730492591858},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5324832797050476},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5184354782104492},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5089080333709717},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.49724557995796204},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4645763337612152},{"id":"https://openalex.org/C95203288","wikidata":"https://www.wikidata.org/wiki/Q221682","display_name":"Semaphore","level":2,"score":0.457735538482666},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4493095874786377},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.44852912425994873},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.42880699038505554},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42443808913230896},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.37953874468803406},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.34906888008117676},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.32773953676223755},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.23462119698524475},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.1853095293045044},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1808655560016632},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1393280327320099},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11095863580703735},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.09919556975364685},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2010.5457237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2335729","is_oa":true,"landing_page_url":"http://porto.polito.it/2335729/1/published_02.4_4.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:porto.polito.it:2335729","is_oa":true,"landing_page_url":"http://porto.polito.it/2335729/1/published_02.4_4.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1764984001","https://openalex.org/W2017503457","https://openalex.org/W2040412273","https://openalex.org/W2080780071","https://openalex.org/W2117876628","https://openalex.org/W2119177714","https://openalex.org/W2130562747","https://openalex.org/W2136360762","https://openalex.org/W2144578269","https://openalex.org/W2147471190","https://openalex.org/W2160642395","https://openalex.org/W2162991651","https://openalex.org/W2169150396","https://openalex.org/W2903691225","https://openalex.org/W4234177455","https://openalex.org/W4241035809","https://openalex.org/W6635487442","https://openalex.org/W6651866598","https://openalex.org/W6654834059","https://openalex.org/W6679474795"],"related_works":["https://openalex.org/W2118508246","https://openalex.org/W3167332351","https://openalex.org/W1534227216","https://openalex.org/W1482095711","https://openalex.org/W2152389059","https://openalex.org/W1482370651","https://openalex.org/W4239256182","https://openalex.org/W2113267301","https://openalex.org/W2161350198","https://openalex.org/W3149530953"],"abstract_inverted_index":{"The":[0],"shared-memory":[1],"model":[2],"has":[3,92,127,145],"been":[4,93,146],"adopted,":[5],"both":[6],"for":[7,73,131],"data":[8],"exchange":[9,58],"as":[10,12,148],"well":[11],"synchronization":[13,38,60],"using":[14],"semaphores":[15],"in":[16,46],"almost":[17],"every":[18,124],"on-chip":[19,68],"multiprocessor":[20],"implementation,":[21],"ranging":[22],"from":[23],"general":[24],"purpose":[25],"chip":[26],"multiprocessors":[27],"(CMPs)":[28],"to":[29,44,49,152],"domain":[30],"specific":[31],"multi-core":[32],"graphics":[33],"processing":[34,64],"units":[35],"(GPUs).":[36],"Low-latency":[37],"is":[39,42],"desirable":[40],"but":[41],"hard":[43],"achieve":[45],"practice":[47],"due":[48],"the":[50,54,63,74,83,142,154],"memory":[51],"hierarchy.":[52],"On":[53],"contrary,":[55],"an":[56],"explicit":[57],"of":[59,113,141,163],"tokens":[61],"among":[62],"elements":[65],"through":[66],"dedicated":[67],"links":[69],"would":[70],"be":[71],"beneficial":[72],"overall":[75],"system":[76,104,164],"performance.":[77],"In":[78,122],"this":[79],"paper":[80],"we":[81],"propose":[82],"Medea":[84,91],"NoC-based":[85],"framework,":[86],"a":[87,96,102,149],"hybrid":[88],"shared-memory/message-passing":[89],"approach.":[90],"modeled":[94],"with":[95],"fast,":[97],"cycle-accurate":[98],"SystemC":[99,125],"implementation":[100,133],"enabling":[101],"fast":[103],"exploration":[105,165],"varying":[106],"several":[107],"parameters":[108],"like":[109],"number":[110],"and":[111,117,119,136,161,166],"types":[112],"cores,":[114],"cache":[115],"size":[116],"policy":[118],"NoC":[120],"features.":[121],"addition,":[123],"block":[126],"its":[128],"RTL":[129],"counterpart":[130],"physical":[132],"on":[134],"FPGAs":[135],"ASICs.":[137],"A":[138],"parallel":[139],"version":[140],"Jacobi":[143],"algorithm":[144],"used":[147],"test":[150],"application":[151],"validate":[153],"methodology.":[155],"Results":[156],"confirm":[157],"expectations":[158],"about":[159],"performance":[160],"effectiveness":[162],"design.":[167]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-02-26T08:16:20.718346","created_date":"2025-10-10T00:00:00"}