{"id":"https://openalex.org/W4248356902","doi":"https://doi.org/10.1109/date.2010.5457236","title":"Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme","display_name":"Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4248356902","doi":"https://doi.org/10.1109/date.2010.5457236"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457236","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457236","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101673000","display_name":"Mingjing Chen","orcid":"https://orcid.org/0000-0001-5987-8772"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mingjing Chen","raw_affiliation_strings":["CSE Department, University of California, San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"CSE Department, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006811625","display_name":"Alex Orailo\u011flu","orcid":"https://orcid.org/0000-0002-6104-3923"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alex Orailoglu","raw_affiliation_strings":["CSE Department, University of California, San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"CSE Department, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101673000"],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":0.4994,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70550255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":null,"first_page":"63","last_page":"68"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.8300167322158813},{"id":"https://openalex.org/keywords/drop","display_name":"Drop (telecommunication)","score":0.7112793326377869},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6503455638885498},{"id":"https://openalex.org/keywords/failure-mode-and-effects-analysis","display_name":"Failure mode and effects analysis","score":0.6291404366493225},{"id":"https://openalex.org/keywords/root-cause","display_name":"Root cause","score":0.575014591217041},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5516388416290283},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4808836281299591},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4273696541786194},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3650529682636261},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22029805183410645}],"concepts":[{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.8300167322158813},{"id":"https://openalex.org/C2781345722","wikidata":"https://www.wikidata.org/wiki/Q5308388","display_name":"Drop (telecommunication)","level":2,"score":0.7112793326377869},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6503455638885498},{"id":"https://openalex.org/C66283442","wikidata":"https://www.wikidata.org/wiki/Q1389268","display_name":"Failure mode and effects analysis","level":2,"score":0.6291404366493225},{"id":"https://openalex.org/C84945661","wikidata":"https://www.wikidata.org/wiki/Q7366567","display_name":"Root cause","level":2,"score":0.575014591217041},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5516388416290283},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4808836281299591},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4273696541786194},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3650529682636261},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22029805183410645},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457236","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457236","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1568407911","https://openalex.org/W1900996732","https://openalex.org/W2018607921","https://openalex.org/W2119691242","https://openalex.org/W2128426877","https://openalex.org/W2156747864","https://openalex.org/W2160621850","https://openalex.org/W2162256736","https://openalex.org/W3144199769","https://openalex.org/W3145605605","https://openalex.org/W4237840841","https://openalex.org/W4242107829","https://openalex.org/W6639759450","https://openalex.org/W7111183471"],"related_works":["https://openalex.org/W2111708921","https://openalex.org/W2248979851","https://openalex.org/W3022244032","https://openalex.org/W4313225938","https://openalex.org/W2034061552","https://openalex.org/W4235433456","https://openalex.org/W4312400951","https://openalex.org/W3115269808","https://openalex.org/W2489202323","https://openalex.org/W4312726176"],"abstract_inverted_index":{"Ever-increasing":[0],"test":[1,42,134,175,193],"mode":[2],"IR-drop":[3,20,51,70,115,154,170,183],"results":[4,161],"in":[5,86,172],"a":[6,18,25,40,46,88,129,133,168,180,190],"significant":[7,32,169],"amount":[8],"of":[9,17,49,58,112],"defect-free":[10],"chips":[11,67,143],"failing":[12,66,142],"at-speed":[13],"testing.":[14],"The":[15,61],"lack":[16],"systematic":[19],"failure":[21,28,53,113,184],"identification":[22,185],"technique":[23,63],"engenders":[24],"highly":[26,181],"increased":[27,192],"analysis":[29],"time/cost":[30],"and":[31,186],"yield":[33,139,187],"loss.":[34],"In":[35],"this":[36],"paper,":[37],"we":[38],"propose":[39],"failure-adaptive":[41],"scheme":[43,135,166],"that":[44,72,90,126,163],"enables":[45,137],"fast":[47],"differentiation":[48],"the":[50,55,59,65,76,92,97,109,146,150,157,164,173],"induced":[52],"from":[54,75,141],"actual":[56,93],"defects":[57,94],"chip.":[60],"proposed":[62,165],"debugs":[64],"using":[68],"low":[69],"vectors":[71,83,99,152],"are":[73,84,100],"custom-generated":[74],"observed":[77],"faulty":[78],"response.":[79],"Since":[80],"these":[81],"special":[82],"designed":[85],"such":[87],"way":[89],"all":[91],"captured":[95],"by":[96,144,149],"original":[98],"still":[101],"manifestable,":[102],"their":[103],"application":[104],"can":[105],"clearly":[106],"pinpoint":[107],"whether":[108],"root":[110],"cause":[111],"is":[114],"or":[116],"not,":[117],"thus":[118,178],"eliminating":[119],"reliance":[120],"on":[121],"an":[122],"intrusive":[123],"debugging":[124,151],"process":[125],"incurs":[127],"quite":[128],"high":[130],"cost.":[131,194],"Such":[132],"further":[136],"effective":[138,182],"recovery":[140,188],"passing":[145],"ones":[147],"validated":[148],"whose":[153],"level":[155],"matches":[156],"functional":[158],"mode.":[159],"Experimental":[160],"show":[162],"delivers":[167],"reduction":[171],"second":[174],"(debugging)":[176],"phase,":[177],"enabling":[179],"at":[189],"slightly":[191]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}