{"id":"https://openalex.org/W4233180362","doi":"https://doi.org/10.1109/date.2010.5457233","title":"Scan based methodology for reliable state retention power gating designs","display_name":"Scan based methodology for reliable state retention power gating designs","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4233180362","doi":"https://doi.org/10.1109/date.2010.5457233"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102897063","display_name":"Sheng Yang","orcid":"https://orcid.org/0000-0001-8063-510X"},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Sheng Yang","raw_affiliation_strings":["School of ECS, University of Southampton, UK"],"affiliations":[{"raw_affiliation_string":"School of ECS, University of Southampton, UK","institution_ids":["https://openalex.org/I43439940"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012783672","display_name":"Bashir M. Al\u2010Hashimi","orcid":"https://orcid.org/0000-0002-3591-1328"},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Bashir M Al-Hashimi","raw_affiliation_strings":["School of ECS, University of Southampton, UK"],"affiliations":[{"raw_affiliation_string":"School of ECS, University of Southampton, UK","institution_ids":["https://openalex.org/I43439940"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032160199","display_name":"David Flynn","orcid":"https://orcid.org/0000-0002-1024-3618"},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Flynn","raw_affiliation_strings":["ARM, Inc., Cambridge, UK"],"affiliations":[{"raw_affiliation_string":"ARM, Inc., Cambridge, UK","institution_ids":["https://openalex.org/I2801109035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107854382","display_name":"Saqib Khursheed","orcid":"https://orcid.org/0000-0002-5720-0607"},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Saqib Khursheed","raw_affiliation_strings":["School of ECS, University of Southampton, UK"],"affiliations":[{"raw_affiliation_string":"School of ECS, University of Southampton, UK","institution_ids":["https://openalex.org/I43439940"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102897063"],"corresponding_institution_ids":["https://openalex.org/I43439940"],"apc_list":null,"apc_paid":null,"fwci":0.25795944,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68392302,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"69","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8585778474807739},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7276393175125122},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5672442317008972},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5639711618423462},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5397276878356934},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.5293322801589966},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5142228603363037},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.4698808491230011},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.46930861473083496},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45359793305397034},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4443832039833069},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4357214570045471},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.42970559000968933},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4185657799243927},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38623929023742676},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35157692432403564},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34821927547454834},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25847694277763367},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19880622625350952},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16851630806922913},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1525573432445526},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12404513359069824},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.11133748292922974},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09138733148574829},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08858507871627808}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8585778474807739},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7276393175125122},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5672442317008972},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5639711618423462},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5397276878356934},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.5293322801589966},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5142228603363037},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.4698808491230011},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.46930861473083496},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45359793305397034},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4443832039833069},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4357214570045471},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.42970559000968933},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4185657799243927},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38623929023742676},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35157692432403564},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34821927547454834},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25847694277763367},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19880622625350952},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16851630806922913},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1525573432445526},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12404513359069824},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11133748292922974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09138733148574829},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08858507871627808},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9200000166893005}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1582019256","https://openalex.org/W2042352336","https://openalex.org/W2053674573","https://openalex.org/W2124276471","https://openalex.org/W2125263803","https://openalex.org/W2126416778","https://openalex.org/W2149421766","https://openalex.org/W4248310916"],"related_works":["https://openalex.org/W2152979262","https://openalex.org/W2546524276","https://openalex.org/W4226239708","https://openalex.org/W2145376025","https://openalex.org/W3127845477","https://openalex.org/W4239594101","https://openalex.org/W2124210802","https://openalex.org/W229101532","https://openalex.org/W2113774150","https://openalex.org/W2005728592"],"abstract_inverted_index":{"Power":[0],"gating":[1,114,188],"is":[2,95,106,130,145,153,178],"an":[3],"effective":[4],"technique":[5],"for":[6,74],"reducing":[7],"leakage":[8],"power":[9,17,113,187],"which":[10,23,63],"involves":[11],"powering":[12],"off":[13],"idle":[14],"circuits":[15,22,38],"through":[16,89,190],"switches,":[18],"but":[19],"those":[20],"power-gated":[21,37,79],"need":[24],"to":[25,43,155],"retain":[26],"their":[27,30],"states":[28],"store":[29],"data":[31,57,100],"in":[32,58,125,182],"state":[33,60,86,90,191],"retention":[34,61,87],"registers.":[35],"When":[36],"are":[39],"switched":[40],"from":[41],"sleep":[42],"active":[44],"mode,":[45],"sudden":[46],"rush":[47],"of":[48,53,78,85,120,139,174,185],"current":[49],"has":[50],"the":[51,55,59,76,83,121,133,140,172,179,183],"potential":[52],"corrupting":[54],"stored":[56],"registers":[62,88],"could":[64],"be":[65],"a":[66,72],"reliability":[67,77],"problem.":[68],"This":[69,94],"paper":[70],"presents":[71],"methodology":[73,105,144],"improving":[75],"designs":[80,189],"by":[81,97],"protecting":[82],"integrity":[84],"monitoring":[91,192],"and":[92,102,112,127,136,149,163,193],"correction.":[93,194],"achieved":[96],"scan":[98],"chain":[99],"encoding":[101],"decoding.":[103],"The":[104,143],"compatible":[107],"with":[108,160,168],"EDA":[109],"tools":[110],"design":[111],"control":[115],"flows.":[116],"A":[117],"detailed":[118],"analysis":[119],"proposed":[122],"methodology's":[123],"capability":[124],"detecting":[126],"correcting":[128],"errors":[129,159,167],"given":[131],"including":[132],"area":[134,184],"overhead":[135],"energy":[137],"consumption":[138],"protection":[141],"circuitry.":[142],"validate":[146],"using":[147],"FPGA":[148],"show":[150],"that":[151],"it":[152],"possible":[154],"correct":[156],"all":[157,165],"single":[158],"Hamming":[161],"code":[162],"detect":[164],"multiple":[166],"CRC-16":[169],"code.":[170],"To":[171],"best":[173],"our":[175],"knowledge":[176],"this":[177],"first":[180],"study":[181],"reliable":[186]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}