{"id":"https://openalex.org/W3148993415","doi":"https://doi.org/10.1109/date.2010.5457230","title":"An efficient distributed memory interface for many-core platform with 3D stacked DRAM","display_name":"An efficient distributed memory interface for many-core platform with 3D stacked DRAM","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3148993415","doi":"https://doi.org/10.1109/date.2010.5457230","mag":"3148993415"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046255006","display_name":"Igor Loi","orcid":"https://orcid.org/0000-0003-3852-4662"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Igor Loi","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5046255006"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":5.6979,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.96486729,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"99","last_page":"104"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8877663612365723},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7384434938430786},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5900921821594238},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4888703227043152},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.45117276906967163},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4337095022201538},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42100638151168823},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3990747630596161},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33120447397232056},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27462655305862427},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06324267387390137}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8877663612365723},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7384434938430786},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5900921821594238},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4888703227043152},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.45117276906967163},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4337095022201538},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42100638151168823},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3990747630596161},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33120447397232056},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27462655305862427},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06324267387390137},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2010.5457230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/95320","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/95320","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7799999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2014189044","https://openalex.org/W2045130493","https://openalex.org/W2071003187","https://openalex.org/W2107304970","https://openalex.org/W2122636510","https://openalex.org/W2123184444","https://openalex.org/W2137893918","https://openalex.org/W2139730616","https://openalex.org/W2155371841","https://openalex.org/W2160642395","https://openalex.org/W3139689176","https://openalex.org/W6680835552"],"related_works":["https://openalex.org/W2094308961","https://openalex.org/W2533585248","https://openalex.org/W4386903460","https://openalex.org/W2806599233","https://openalex.org/W2130233920","https://openalex.org/W2473808647","https://openalex.org/W4389476207","https://openalex.org/W2125880695","https://openalex.org/W2134643927","https://openalex.org/W2120093897"],"abstract_inverted_index":{"Historically,":[0],"processor":[1],"performance":[2],"has":[3],"increased":[4],"at":[5],"a":[6,34,137],"much":[7],"faster":[8],"rate":[9],"than":[10],"that":[11,159],"of":[12,40,96,119,123,173],"main":[13],"memory":[14,24,42,48,66,80,92,102,178],"and":[15,52,77,115,180],"up-coming":[16],"NoC-based":[17],"many-core":[18],"architectures":[19],"are":[20],"further":[21],"tightening":[22],"the":[23,60,91,113,120,130,149,168,187],"bottleneck.":[25],"3D":[26],"integration":[27],"based":[28],"on":[29,94],"TSV":[30],"technology":[31],"may":[32],"provide":[33],"solution,":[35],"as":[36,165],"it":[37],"enables":[38],"stacking":[39],"multiple":[41],"layers,":[43],"with":[44,143,171],"orders-of-magnitude":[45],"increase":[46],"in":[47],"interface":[49,62,81,86,134],"bandwidth,":[50],"speed":[51],"energy":[53],"efficiency.":[54],"To":[55],"fully":[56],"exploit":[57],"this":[58,71],"potential,":[59],"architectural":[61],"to":[63,90,105,148,163,167],"vertically":[64],"stacked":[65],"must":[67],"be":[68],"streamlined.":[69],"In":[70],"paper":[72],"we":[73],"present":[74],"an":[75],"efficient":[76],"flexible":[78],"distributed":[79],"for":[82,176,183],"3D-stacked":[83],"DRAM.":[84],"Our":[85],"ensures":[87],"ultra-low-latency":[88],"access":[89,185],"modules":[93,108],"top":[95],"each":[97],"processing":[98],"element":[99],"(vertically":[100],"local":[101,107],"neighborhoods).":[103],"Communication":[104],"these":[106],"do":[109],"not":[110],"travel":[111],"through":[112,186],"NoC":[114],"takes":[116],"full":[117],"advantage":[118],"lower":[121],"latency":[122],"vertical":[124],"interconnect,":[125],"thus":[126],"speeding":[127],"up":[128],"significantly":[129],"common":[131],"case.":[132],"The":[133],"still":[135],"supports":[136],"convenient":[138],"global":[139],"address":[140],"space":[141],"abstraction":[142],"high-latency":[144],"remote":[145,184],"access,":[146,179],"due":[147],"slower":[150],"horizontal":[151],"interconnect.":[152],"Experimental":[153],"results":[154],"demonstrate":[155],"significant":[156],"bandwidth":[157],"improvement":[158],"ranges":[160],"from":[161],"1.44\u00d7":[162],"7.40\u00d7":[164],"compared":[166],"JEDEC":[169],"standard,":[170],"peaks":[172],"4.53":[174],"GB/s":[175],"direct":[177],"850":[181],"MB/s":[182],"NoC.":[188]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}