{"id":"https://openalex.org/W3148613010","doi":"https://doi.org/10.1109/date.2010.5457227","title":"Efficient OpenMP data mapping for multicore platforms with vertically stacked memory","display_name":"Efficient OpenMP data mapping for multicore platforms with vertically stacked memory","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3148613010","doi":"https://doi.org/10.1109/date.2010.5457227","mag":"3148613010"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1171887","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061145921","display_name":"Andrea Marongiu","orcid":"https://orcid.org/0000-0003-1010-4762"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Andrea Marongiu","raw_affiliation_strings":["DEIS, Universit\u00e0 di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062549550","display_name":"Martino Ruggiero","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Martino Ruggiero","raw_affiliation_strings":["DEIS, Universit\u00e0 di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS, Universit\u00e0 di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5061145921"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":0.5873,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75276853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"110"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8271017670631409},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.7701114416122437},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.611937403678894},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.605573296546936},{"id":"https://openalex.org/keywords/spmd","display_name":"SPMD","score":0.6029034852981567},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5852548480033875},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5714288949966431},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5610092878341675},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4934500753879547},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48810896277427673},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.47767361998558044},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.4574422836303711},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.43042463064193726},{"id":"https://openalex.org/keywords/data-structure","display_name":"Data structure","score":0.4228723347187042},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24615603685379028},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17968961596488953},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.17470118403434753},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.1215679943561554},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.12058940529823303},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09402456879615784}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8271017670631409},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.7701114416122437},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.611937403678894},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.605573296546936},{"id":"https://openalex.org/C7042729","wikidata":"https://www.wikidata.org/wiki/Q2289219","display_name":"SPMD","level":2,"score":0.6029034852981567},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5852548480033875},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5714288949966431},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5610092878341675},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4934500753879547},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48810896277427673},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.47767361998558044},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.4574422836303711},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.43042463064193726},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.4228723347187042},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24615603685379028},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17968961596488953},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.17470118403434753},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.1215679943561554},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.12058940529823303},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09402456879615784},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2010.5457227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unimore.it:11380/1171887","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171887","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1171887","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171887","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2002907208","https://openalex.org/W2028641195","https://openalex.org/W2082499523","https://openalex.org/W2092388465","https://openalex.org/W2094134703","https://openalex.org/W2100212269","https://openalex.org/W2103227834","https://openalex.org/W2126952393","https://openalex.org/W2131413854","https://openalex.org/W2143807959","https://openalex.org/W2153215457","https://openalex.org/W2159192094","https://openalex.org/W3145506805","https://openalex.org/W3147007208","https://openalex.org/W3147224349","https://openalex.org/W4230104114","https://openalex.org/W4237161200","https://openalex.org/W6676317001","https://openalex.org/W6682540009"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W2389264397","https://openalex.org/W1985165680","https://openalex.org/W4245497162","https://openalex.org/W4239431034","https://openalex.org/W2353146130","https://openalex.org/W2020419141","https://openalex.org/W2098134458","https://openalex.org/W2270787918","https://openalex.org/W2117348221"],"abstract_inverted_index":{"Emerging":[0],"TSV-based":[1],"3D":[2],"integration":[3],"technologies":[4],"have":[5],"shown":[6],"great":[7],"promise":[8],"to":[9,35,74,93,106],"overcome":[10],"scalability":[11],"limitations":[12],"in":[13],"2D":[14],"designs":[15],"by":[16],"stacking":[17],"multiple":[18,70],"memory":[19,62,72,96],"dies":[20],"on":[21,49,57,97,121],"top":[22,98],"of":[23,40,67,99,109,113],"a":[24,80],"many-core":[25],"die.":[26],"Application":[27],"software":[28],"developers":[29],"need":[30],"programming":[31,81],"models":[32],"and":[33,116],"tools":[34],"fully":[36],"exploit":[37],"the":[38,94,100,110,122],"potential":[39],"vertically":[41],"stacked":[42],"memory.":[43],"In":[44],"this":[45],"work,":[46],"we":[47],"focus":[48],"efficient":[50],"data":[51,68],"mapping":[52],"for":[53,117],"SPMD":[54],"parallel":[55],"applications":[56],"an":[58],"explicitly":[59],"managed":[60],"3D-stacked":[61,95],"hierarchy,":[63],"which":[64],"requires":[65],"placement":[66],"across":[69],"vertical":[71,114],"stacks":[73],"be":[75],"carefully":[76],"optimized.":[77],"We":[78],"propose":[79],"framework":[82],"with":[83],"compiler":[84],"support":[85],"that":[86,102],"enables":[87],"array":[88],"partitioning.":[89],"Partitions":[90],"are":[91],"mapped":[92],"processor":[101],"mostly":[103],"accesses":[104],"it":[105],"take":[107],"advantage":[108],"lower":[111],"latencies":[112],"interconnect":[115],"minimizing":[118],"high-latency":[119],"traffic":[120],"horizontal":[123],"plane.":[124]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
