{"id":"https://openalex.org/W3143819208","doi":"https://doi.org/10.1109/date.2010.5457194","title":"An RDL-configurable 3D memory tier to replace on-chip SRAM","display_name":"An RDL-configurable 3D memory tier to replace on-chip SRAM","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3143819208","doi":"https://doi.org/10.1109/date.2010.5457194","mag":"3143819208"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457194","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057153631","display_name":"Marco Facchini","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Marco Facchini","raw_affiliation_strings":["ESAT MICAS Katholieke University Leuven, Heverlee, Belgium","IMEC InterUniversity Microelectronics Center, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESAT MICAS Katholieke University Leuven, Heverlee, Belgium","institution_ids":["https://openalex.org/I99464096"]},{"raw_affiliation_string":"IMEC InterUniversity Microelectronics Center, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108406914","display_name":"Pol Marchal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Pol Marchal","raw_affiliation_strings":["IMEC InterUniversity Microelectronics Center, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC InterUniversity Microelectronics Center, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033235745","display_name":"Francky Catthoor","orcid":"https://orcid.org/0000-0002-3599-8515"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Francky Catthoor","raw_affiliation_strings":["IMEC InterUniversity Microelectronics Center, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC InterUniversity Microelectronics Center, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076274517","display_name":"Wim Dehaene","orcid":"https://orcid.org/0000-0002-6792-7965"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Wim Dehaene","raw_affiliation_strings":["ESAT MICAS Katholieke University Leuven, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESAT MICAS Katholieke University Leuven, Heverlee, Belgium","institution_ids":["https://openalex.org/I99464096"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7802,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.86086438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"291","last_page":"294"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7553322315216064},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6619465351104736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5888323187828064},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.48532384634017944},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4829089641571045},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.456347793340683},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.44568127393722534},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3455427289009094},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33764636516571045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2897389531135559},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17669034004211426},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16550958156585693}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7553322315216064},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6619465351104736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5888323187828064},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.48532384634017944},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4829089641571045},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.456347793340683},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.44568127393722534},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3455427289009094},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33764636516571045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2897389531135559},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17669034004211426},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16550958156585693},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457194","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457194","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2135520189","https://openalex.org/W2162968317","https://openalex.org/W3144500201","https://openalex.org/W3147007208","https://openalex.org/W4239250096","https://openalex.org/W4240650415"],"related_works":["https://openalex.org/W2334181344","https://openalex.org/W2401095501","https://openalex.org/W2362277122","https://openalex.org/W2558276258","https://openalex.org/W2934889147","https://openalex.org/W4293054943","https://openalex.org/W4249130715","https://openalex.org/W2526783553","https://openalex.org/W2295799647","https://openalex.org/W4214748026"],"abstract_inverted_index":{"In":[0,70,132],"a":[1,38,75,102],"conventional":[2],"SoC":[3],"designs,":[4],"on-chip":[5],"memories":[6,25],"occupy":[7],"more":[8,125],"than":[9,126],"the":[10,13,20,34,62,83,88,110,113],"50%":[11],"of":[12,22,61,128],"total":[14],"die":[15],"area.":[16],"3D":[17],"technology":[18],"enables":[19],"distribution":[21],"logic":[23],"and":[24,59,98,101],"on":[26],"separate":[27],"stacked":[28],"dies":[29],"(tiers).":[30],"This":[31],"allows":[32],"redesigning":[33],"memory":[35,78,96],"tier":[36,79],"as":[37],"configurable":[39,77],"product":[40],"to":[41,66,81,87,109,118],"be":[42],"used":[43],"in":[44],"multiple":[45],"system":[46],"designs.":[47],"Previously":[48],"proposed":[49,114],"dynamic":[50,111],"re-configurable":[51],"solutions":[52],"demonstrate":[53],"strong":[54],"dependence":[55],"between":[56],"read":[57],"latency":[58],"dimensions":[60],"mapped":[63],"memory,":[64],"leading":[65],"potential":[67],"performance":[68],"limitations.":[69],"this":[71],"paper":[72],"we":[73],"propose":[74],"one-time":[76],"designed":[80],"minimize":[82],"performances":[84],"overhead":[85],"due":[86],"commodity.":[89],"Flexible":[90],"configuration":[91],"is":[92],"enabled":[93],"by":[94],"smart":[95],"macros":[97],"I/Os":[99],"organization":[100],"customizable":[103],"redistribution":[104],"layer":[105],"routing.":[106],"With":[107],"respect":[108],"re-configurability,":[112],"design":[115],"offers":[116],"up":[117],"40%":[119],"faster":[120],"access":[121],"time,":[122],"while":[123],"saving":[124],"10%":[127],"energy":[129],"per":[130],"access.":[131],"addition":[133],"production":[134],"cost":[135],"trade":[136],"offs":[137],"are":[138],"analyzed.":[139]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
