{"id":"https://openalex.org/W4210626857","doi":"https://doi.org/10.1109/date.2010.5457188","title":"Implementing digital logic with sinusoidal supplies","display_name":"Implementing digital logic with sinusoidal supplies","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4210626857","doi":"https://doi.org/10.1109/date.2010.5457188"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046473766","display_name":"Kalyana C. Bollapalli","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kalyana C Bollapalli","raw_affiliation_strings":["Department of ECE, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021685706","display_name":"Sunil P. Khatri","orcid":"https://orcid.org/0000-0001-7134-9929"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sunil P Khatri","raw_affiliation_strings":["Department of ECE, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073866549","display_name":"L\u00e1szl\u00f3 B. Kish","orcid":"https://orcid.org/0000-0002-8917-954X"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Laszlo B Kish","raw_affiliation_strings":["Department of ECE, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5046473766"],"corresponding_institution_ids":["https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":0.7122,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.7620131,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"315","last_page":"318"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13748","display_name":"Advanced Statistical Modeling Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13748","display_name":"Advanced Statistical Modeling Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9835000038146973,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.968999981880188,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6828771829605103},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6141621470451355},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6095346212387085},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.602414071559906},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5839048624038696},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.5378227829933167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4831785261631012},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46607542037963867},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4421907067298889},{"id":"https://openalex.org/keywords/logic-analyzer","display_name":"Logic analyzer","score":0.428561270236969},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36637938022613525},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.35273507237434387},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3429320454597473},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3259618878364563},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22786086797714233},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1910756230354309},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17073890566825867},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.09882938861846924},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08732524514198303}],"concepts":[{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6828771829605103},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6141621470451355},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6095346212387085},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.602414071559906},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5839048624038696},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.5378227829933167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4831785261631012},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46607542037963867},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4421907067298889},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.428561270236969},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36637938022613525},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.35273507237434387},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3429320454597473},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3259618878364563},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22786086797714233},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1910756230354309},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17073890566825867},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.09882938861846924},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08732524514198303},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1984101209","https://openalex.org/W2079092477","https://openalex.org/W2120170977","https://openalex.org/W2127744385","https://openalex.org/W2155874470","https://openalex.org/W2157488385","https://openalex.org/W4246466063","https://openalex.org/W6678804247"],"related_works":["https://openalex.org/W2155174752","https://openalex.org/W2118487491","https://openalex.org/W2142702094","https://openalex.org/W2006855068","https://openalex.org/W1601832081","https://openalex.org/W2890889888","https://openalex.org/W2132673349","https://openalex.org/W2160304012","https://openalex.org/W2158157809","https://openalex.org/W321873635"],"abstract_inverted_index":{"In":[0],"this":[1,130,185,189],"paper,":[2],"a":[3,57,69,77,110,115,159,165,172],"new":[4],"type":[5],"of":[6,22,45,50,72,98,118,129,150,170],"combinational":[7],"logic":[8,40,63,78,89,92,173],"circuit":[9,140],"realization":[10],"is":[11,175],"presented.":[12],"Logic":[13],"values":[14,44,64],"are":[15,26],"implemented":[16],"as":[17,65],"sinusoidal":[18,66,86,148],"signals.":[19],"Sinusoidal":[20],"signals":[21,67,87,100,149],"the":[23,39,85,151],"same":[24,152],"frequency":[25,153],"phase":[27,156],"shifted":[28],"by":[29],"\u00bf":[30],"to":[31,55,96,146,193],"destructively":[32],"interfere":[33],"with":[34,101],"each":[35],"other,":[36],"and":[37,42,91,132,154],"represent":[38],"0":[41,90],"1":[43,93],"Boolean":[46],"Logic.":[47],"These":[48],"properties":[49],"sinusoids":[51,105],"can":[52,82,133],"be":[53,107],"used":[54,192],"identify":[56],"signal":[58],"without":[59],"ambiguity.":[60],"Thus,":[61],"representing":[62],"yields":[68,198],"realizable":[70],"system":[71],"logic.":[73,121],"The":[74,182],"paper":[75,186],"presents":[76],"gate":[79],"family":[80,174],"that":[81,188],"operate":[83],"using":[84],"for":[88],"values.":[94],"Due":[95],"orthogonality":[97],"sinusoid":[99],"different":[102],"frequencies,":[103],"multiple":[104],"could":[106,126],"transmitted":[108],"on":[109],"single":[111,160],"wire.":[112],"This":[113],"provides":[114],"natural":[116],"way":[117],"implementing":[119],"multilevel":[120],"Signals":[122],"traveling":[123],"long":[124],"distances":[125],"take":[127],"advantage":[128,169],"fact":[131],"share":[134],"interconnect":[135],"lines.":[136],"Recent":[137],"research":[138],"in":[139,164,184,201],"design":[141],"has":[142],"made":[143],"it":[144],"possible":[145],"harvest":[147],"180\u00b0":[155],"difference":[157],"from":[158,178],"resonant":[161],"clock":[162],"ring":[163],"distributed":[166],"manner.":[167],"Other":[168],"such":[171],"its":[176],"immunity":[177],"external":[179],"additive":[180],"noise.":[181],"experiments":[183],"indicate":[187],"paradigm,":[190],"when":[191],"implement":[194],"binary":[195],"valued":[196],"logic,":[197],"an":[199],"improvement":[200],"switching":[202],"(dynamic)":[203],"power.":[204]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
