{"id":"https://openalex.org/W3151144990","doi":"https://doi.org/10.1109/date.2010.5457187","title":"Low-power FinFET circuit synthesis using surface orientation optimization","display_name":"Low-power FinFET circuit synthesis using surface orientation optimization","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3151144990","doi":"https://doi.org/10.1109/date.2010.5457187","mag":"3151144990"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457187","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000714311","display_name":"Prateek Mishra","orcid":"https://orcid.org/0000-0003-1276-1678"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prateek Mishra","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086131079","display_name":"Niraj K. Jha","orcid":"https://orcid.org/0000-0002-1539-0369"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Niraj K Jha","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":3.5604,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.94103805,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"311","last_page":"314"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6329165101051331},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5691332221031189},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5641366839408875},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5405513048171997},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.518939733505249},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47567954659461975},{"id":"https://openalex.org/keywords/plane","display_name":"Plane (geometry)","score":0.44982051849365234},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4280078411102295},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.42620405554771423},{"id":"https://openalex.org/keywords/orientation","display_name":"Orientation (vector space)","score":0.42606717348098755},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4007246494293213},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2519921660423279},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24273478984832764},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21454209089279175},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17123296856880188},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.06815844774246216}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6329165101051331},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5691332221031189},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5641366839408875},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5405513048171997},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.518939733505249},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47567954659461975},{"id":"https://openalex.org/C17825722","wikidata":"https://www.wikidata.org/wiki/Q17285","display_name":"Plane (geometry)","level":2,"score":0.44982051849365234},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4280078411102295},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.42620405554771423},{"id":"https://openalex.org/C16345878","wikidata":"https://www.wikidata.org/wiki/Q107472979","display_name":"Orientation (vector space)","level":2,"score":0.42606717348098755},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4007246494293213},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2519921660423279},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24273478984832764},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21454209089279175},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17123296856880188},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.06815844774246216},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457187","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1999483775","https://openalex.org/W2044782068","https://openalex.org/W2058283199","https://openalex.org/W2105874609","https://openalex.org/W2113013533","https://openalex.org/W2120985183","https://openalex.org/W2131427072","https://openalex.org/W2160948307","https://openalex.org/W4249985154","https://openalex.org/W6650061924","https://openalex.org/W6678049473"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2909211499","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W3119688974"],"abstract_inverted_index":{"FinFETs":[0,119],"with":[1],"channel":[2,88],"surface":[3,74],"along":[4],"theplane":[5,26],"can":[6,34,51],"be":[7,35,52],"easily":[8],"fabricated":[9],"by":[10,14,37],"rotating":[11],"the":[12,31,44,130,159],"fins":[13],"45\u00b0":[15],"from":[16],"theplane.":[17],"By":[18],"designing":[19],"logic":[20,80],"gates,":[21,151],"which":[22,83],"have":[23],"pFinFETs":[24],"in":[25,29,49,58,102,120],"and":[27,108],"nFinFETs":[28],"theplane,":[30],"gate":[32],"delay":[33,50,107,154],"reduced":[36,56],"as":[38,40],"much":[39],"14%,":[41],"compared":[42],"to":[43,104,123],"conventionallogic":[45],"gates.":[46],"The":[47],"reduction":[48],"traded":[53],"off":[54],"for":[55,90,129],"power":[57,109],"FinFET":[59,87],"circuits.":[60,93],"In":[61],"this":[62],"paper,":[63],"we":[64],"propose":[65],"a":[66,97,138],"low-power":[67,92,131],"FinFET-based":[68],"circuit":[69],"synthesis":[70],"methodology":[71,143],"based":[72,99,141],"on":[73,85],"orientation":[75],"optimization.":[76],"We":[77,94,111,136],"study":[78],"various":[79],"design":[81,112],"styles,":[82],"depend":[84],"different":[86,121],"orientations,":[89],"synthesizing":[91],"use":[95,137],"BSIM,":[96],"process/physics":[98],"double-gate":[100],"model":[101],"HSPICE,":[103],"derive":[105],"accurate":[106,126],"estimates.":[110],"layouts":[113],"of":[114,149,161],"standard":[115],"library":[116],"cells":[117],"containing":[118],"orientations":[122],"obtain":[124],"an":[125],"area":[127],"estimate":[128],"synthesized":[132],"netlists":[133],"after":[134],"place-and-route.":[135],"linear":[139],"programming":[140],"optimization":[142],"that":[144],"gives":[145],"power-optimized":[146],"netlists,":[147],"consisting":[148],"oriented":[150],"at":[152],"tight":[153],"constraints.":[155],"Experimental":[156],"results":[157],"demonstrate":[158],"efficacy":[160],"our":[162],"scheme.":[163]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
