{"id":"https://openalex.org/W3142366035","doi":"https://doi.org/10.1109/date.2010.5457136","title":"Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations","display_name":"Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3142366035","doi":"https://doi.org/10.1109/date.2010.5457136","mag":"3142366035"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101567890","display_name":"Aline Vieira de Mello","orcid":"https://orcid.org/0000-0001-6589-8518"},"institutions":[{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Aline Mello","raw_affiliation_strings":["Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006650379","display_name":"Isaac Maia","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Isaac Maia","raw_affiliation_strings":["Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082950212","display_name":"Alain Greiner","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Alain Greiner","raw_affiliation_strings":["Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023748893","display_name":"Fran\u00e7ois P\u00eacheux","orcid":"https://orcid.org/0000-0002-4118-8690"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Francois Pecheux","raw_affiliation_strings":["Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"Lip6-Laboratoire d'Informatique de Paris 6, Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101567890"],"corresponding_institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"],"apc_list":null,"apc_paid":null,"fwci":6.8899,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.96885161,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11195","display_name":"Simulation Techniques and Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},"topics":[{"id":"https://openalex.org/T11195","display_name":"Simulation Techniques and Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9180009365081787},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8490967750549316},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8487213850021362},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8165042400360107},{"id":"https://openalex.org/keywords/virtual-prototyping","display_name":"Virtual prototyping","score":0.6103105545043945},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.6017261147499084},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5902965664863586},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5240787863731384},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.522768497467041},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5074824690818787},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.46576499938964844},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46505388617515564},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.3881547451019287},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.30392366647720337},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.13260895013809204}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9180009365081787},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8490967750549316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8487213850021362},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8165042400360107},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.6103105545043945},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.6017261147499084},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5902965664863586},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5240787863731384},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.522768497467041},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5074824690818787},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.46576499938964844},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46505388617515564},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3881547451019287},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.30392366647720337},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.13260895013809204}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2010.5457136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00748083v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00748083","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DATE 2010 - Design, Automation & Test in Europe Conference & Exhibition, Mar 2010, Dresden, Germany. pp.606-609","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1510187019","https://openalex.org/W1560585010","https://openalex.org/W2044512256","https://openalex.org/W2087064593","https://openalex.org/W2089867526","https://openalex.org/W2147780001"],"related_works":["https://openalex.org/W2007493856","https://openalex.org/W1581055755","https://openalex.org/W4230458348","https://openalex.org/W2149449165","https://openalex.org/W3198758847","https://openalex.org/W1934552808","https://openalex.org/W2099675346","https://openalex.org/W2119788505","https://openalex.org/W4238487776","https://openalex.org/W1576344679"],"abstract_inverted_index":{"The":[0,16,65,89,108],"simulation":[1,25,68,114],"speed":[2],"is":[3,75,91,110],"a":[4,71,80,92,111,122,130,134,138],"key":[5],"issue":[6],"in":[7],"virtual":[8,126],"prototyping":[9],"of":[10,41,63],"Multi-Processors":[11],"System":[12],"on":[13,121,129],"Chip":[14],"(MPSoCs).":[15],"SystemC":[17,67],"TLM2.0":[18],"(Transaction":[19,102],"Level":[20,103],"Modeling)":[21],"approach":[22],"accelerates":[23],"the":[24,34,53,77],"by":[26,46],"using":[27],"Interface":[28],"Method":[29],"Calls":[30],"(IMC)":[31],"to":[32],"implement":[33],"communications":[35],"between":[36],"hardware":[37],"components.":[38],"Another":[39],"source":[40],"speedup":[42],"can":[43],"be":[44],"exploited":[45],"parallel":[47,81,113],"simulation.":[48,82,140],"Multi-core":[49],"workstations":[50,57],"are":[51],"becoming":[52],"mainstream,":[54],"and":[55],"SMP":[56],"will":[58],"soon":[59],"contain":[60],"several":[61],"tens":[62],"cores.":[64],"standard":[66],"engine":[69],"uses":[70],"centralized":[72],"scheduler,":[73],"that":[74],"clearly":[76],"bottleneck":[78],"for":[79,96],"This":[83],"paper":[84],"has":[85],"two":[86],"main":[87],"contributions.":[88],"first":[90],"general":[93],"modeling":[94],"strategy":[95],"shared":[97],"memory":[98],"MPSoCs,":[99],"called":[100,116],"TLM-DT":[101],"Modeling":[104],"with":[105],"Distributed":[106],"Time).":[107],"second":[109],"truly":[112],"engine,":[115],"SystemC-SMP.":[117],"First":[118],"experimental":[119],"results":[120],"40":[123],"processor":[124],"MPSoC":[125],"prototype":[127],"running":[128],"dual-core":[131],"workstation":[132],"demonstrate":[133],"1.8":[135],"speedup,":[136],"versus":[137],"sequential":[139]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":8}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}