{"id":"https://openalex.org/W4238342346","doi":"https://doi.org/10.1109/date.2010.5457049","title":"Optimizing equivalence checking for behavioral synthesis","display_name":"Optimizing equivalence checking for behavioral synthesis","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4238342346","doi":"https://doi.org/10.1109/date.2010.5457049"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033550397","display_name":"Kecheng Hao","orcid":null},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kecheng Hao","raw_affiliation_strings":["Department of Computer Science, Portland State University, Portland, OR, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106551350","display_name":"Fei Xie","orcid":"https://orcid.org/0000-0002-7324-3287"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fei Xie","raw_affiliation_strings":["Department of Computer Science, Portland State University, Portland, OR, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068991400","display_name":"Sandip Ray","orcid":"https://orcid.org/0000-0002-8671-5052"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandip Ray","raw_affiliation_strings":["Department of Computer Sciences, University of Texas, Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052037169","display_name":"Jin Yang","orcid":"https://orcid.org/0000-0002-4372-926X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Yang","raw_affiliation_strings":["Strategic CAD Laboratories, DTS, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratories, DTS, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5033550397"],"corresponding_institution_ids":["https://openalex.org/I126345244"],"apc_list":null,"apc_paid":null,"fwci":1.6726,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.85205543,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"5123","issue":null,"first_page":"1500","last_page":"1505"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.8435640335083008},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.765386700630188},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.7040605545043945},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6648869514465332},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.6168100833892822},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6019743084907532},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5678635835647583},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42136651277542114},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3860783278942108},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36200788617134094},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34531331062316895},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21941933035850525},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.10530346632003784},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10228681564331055}],"concepts":[{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.8435640335083008},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.765386700630188},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.7040605545043945},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6648869514465332},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.6168100833892822},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6019743084907532},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5678635835647583},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42136651277542114},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3860783278942108},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36200788617134094},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34531331062316895},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21941933035850525},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.10530346632003784},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10228681564331055},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1485629610","https://openalex.org/W1506441957","https://openalex.org/W1567363020","https://openalex.org/W1973665222","https://openalex.org/W2003427390","https://openalex.org/W2112643551","https://openalex.org/W2122890990","https://openalex.org/W2133226426","https://openalex.org/W2156116570","https://openalex.org/W2987907651","https://openalex.org/W4230796557","https://openalex.org/W4241530675","https://openalex.org/W4251912342","https://openalex.org/W4253178675","https://openalex.org/W6630427482","https://openalex.org/W6651014287","https://openalex.org/W6672572153","https://openalex.org/W6678770294"],"related_works":["https://openalex.org/W2117120663","https://openalex.org/W1532304424","https://openalex.org/W2116137315","https://openalex.org/W4283699709","https://openalex.org/W2004144979","https://openalex.org/W2122228234","https://openalex.org/W2895905110","https://openalex.org/W1537651185","https://openalex.org/W1583869287","https://openalex.org/W2365988016"],"abstract_inverted_index":{"Behavioral":[0],"synthesis":[1],"is":[2],"the":[3,33,37,50],"compilation":[4],"of":[5,19,24,36,56,61,63,65],"an":[6,12],"Electronic":[7],"system-level":[8],"(ESL)":[9],"design":[10],"into":[11],"RTL":[13,25],"implementation.":[14],"We":[15],"present":[16],"a":[17],"suite":[18],"optimizations":[20,31,51],"for":[21],"equivalence":[22,54],"checking":[23,55],"generated":[26],"through":[27],"behavioral":[28],"synthesis.":[29],"The":[30],"exploit":[32],"high-level":[34],"structure":[35],"ESL":[38],"description":[39],"to":[40],"ameliorate":[41],"verification":[42],"complexity.":[43],"Experiments":[44],"on":[45],"representative":[46],"benchmarks":[47],"indicate":[48],"that":[49],"can":[52],"handle":[53],"synthesized":[57],"designs":[58],"with":[59],"tens":[60],"thousands":[62],"lines":[64],"RTL.":[66]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
