{"id":"https://openalex.org/W4248132667","doi":"https://doi.org/10.1109/date.2010.5457045","title":"A general method to make multi-clock system deterministic","display_name":"A general method to make multi-clock system deterministic","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4248132667","doi":"https://doi.org/10.1109/date.2010.5457045"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114010526","display_name":"Menghao Su","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Menghao Su","raw_affiliation_strings":["Chinese Academy of Sciences, Beijing, China","Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036492388","display_name":"Yunji Chen","orcid":"https://orcid.org/0000-0003-3925-5185"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yunji Chen","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017334961","display_name":"Xiang Gao","orcid":"https://orcid.org/0000-0003-3618-043X"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiang Gao","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5114010526"],"corresponding_institution_ids":["https://openalex.org/I19820366","https://openalex.org/I4210090176"],"apc_list":null,"apc_paid":null,"fwci":0.9987,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.7952202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1480","last_page":"1485"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9688000082969666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9688000082969666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9671000242233276,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9314000010490417,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8132590055465698},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7443065643310547},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7408822178840637},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7193441390991211},{"id":"https://openalex.org/keywords/nondeterministic-algorithm","display_name":"Nondeterministic algorithm","score":0.7186894416809082},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.6924906969070435},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6500881314277649},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6120907068252563},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6010702252388},{"id":"https://openalex.org/keywords/vector-clock","display_name":"Vector clock","score":0.5920950174331665},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5794403553009033},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.49639207124710083},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4800735116004944},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.4183589816093445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39833810925483704},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.39036622643470764},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2920721173286438},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2666357755661011},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24872943758964539},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22661125659942627},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0968187153339386},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.07637682557106018}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8132590055465698},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7443065643310547},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7408822178840637},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7193441390991211},{"id":"https://openalex.org/C176181172","wikidata":"https://www.wikidata.org/wiki/Q3490301","display_name":"Nondeterministic algorithm","level":2,"score":0.7186894416809082},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.6924906969070435},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6500881314277649},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6120907068252563},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6010702252388},{"id":"https://openalex.org/C52563298","wikidata":"https://www.wikidata.org/wiki/Q1413349","display_name":"Vector clock","level":5,"score":0.5920950174331665},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5794403553009033},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.49639207124710083},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4800735116004944},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.4183589816093445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39833810925483704},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.39036622643470764},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2920721173286438},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2666357755661011},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24872943758964539},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22661125659942627},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0968187153339386},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.07637682557106018},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2032829170","https://openalex.org/W2080780071","https://openalex.org/W2099034654","https://openalex.org/W2126647846","https://openalex.org/W2129938370","https://openalex.org/W2129981070","https://openalex.org/W2131053137","https://openalex.org/W2166661626","https://openalex.org/W2170454670","https://openalex.org/W3136117375","https://openalex.org/W6630742994"],"related_works":["https://openalex.org/W1497331638","https://openalex.org/W2787237207","https://openalex.org/W4231008241","https://openalex.org/W2125201667","https://openalex.org/W2163637408","https://openalex.org/W3150661190","https://openalex.org/W2411759562","https://openalex.org/W2617666058","https://openalex.org/W2083095101","https://openalex.org/W3093058274"],"abstract_inverted_index":{"Nondeterminism":[0],"of":[1,31,45,114],"multi-clock":[2,139],"systems":[3],"often":[4],"complicates":[5],"various":[6,83],"system":[7,24],"validation":[8],"processes":[9],"such":[10],"as":[11],"post":[12],"silicon":[13],"debugging":[14],"and":[15,26,90],"at-speed":[16],"testing,":[17],"which":[18,96],"has":[19],"brought":[20,133],"many":[21],"difficulties":[22],"to":[23,49,59,80,82],"designers":[25],"testers.":[27],"The":[28],"major":[29],"source":[30],"nondeterministic":[32],"behaviors":[33],"is":[34,141],"clock":[35,65,84],"domain":[36,66],"crossing,":[37],"because":[38],"the":[39,43,61,77,106,112,130],"clocks":[40],"that":[41,129],"determine":[42],"timing":[44],"events":[46],"are":[47,102],"sensitive":[48],"variations.":[50],"In":[51],"this":[52],"paper,":[53],"we":[54,119],"propose":[55],"a":[56,91,123],"general":[57],"method":[58,69,116,136],"eliminate":[60],"nondeterminism":[62],"resulted":[63],"from":[64],"crossing.":[67],"This":[68],"does":[70],"not":[71],"assume":[72],"any":[73],"specific":[74],"relationship":[75],"among":[76],"clocks.":[78],"Instead,":[79],"adapt":[81],"conditions,":[85],"an":[86],"automatic":[87],"configuration":[88],"procedure":[89],"periodic":[92],"error":[93],"canceling":[94],"mechanism,":[95],"only":[97],"require":[98],"trivial":[99],"hardware":[100],"support,":[101],"proposed":[103],"by":[104,134],"analyzing":[105],"deterministic":[107],"boundaries":[108],"theoretically.":[109],"To":[110],"demonstrate":[111],"applicability":[113],"our":[115,135],"in":[117],"practice,":[118],"implement":[120],"it":[121],"on":[122],"FPGA":[124],"platform.":[125],"Experiment":[126],"results":[127],"validate":[128],"performance":[131],"loss":[132],"over":[137],"conventional":[138],"FIFO":[140],"less":[142],"than":[143],"2%.":[144]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}