{"id":"https://openalex.org/W4231794298","doi":"https://doi.org/10.1109/date.2010.5457020","title":"An on-chip clock generation scheme for faster-than-at-speed delay testing","display_name":"An on-chip clock generation scheme for faster-than-at-speed delay testing","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4231794298","doi":"https://doi.org/10.1109/date.2010.5457020"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457020","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457020","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111796111","display_name":"Songwei Pei","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Songwei Pei","raw_affiliation_strings":["Chinese Academy of Sciences, Beijing, China","Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100768288","display_name":"Huawei Li","orcid":"https://orcid.org/0000-0001-8082-4218"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huawei Li","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023380073","display_name":"Xiaowei Li","orcid":"https://orcid.org/0000-0002-0874-814X"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaowei Li","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111796111"],"corresponding_institution_ids":["https://openalex.org/I19820366","https://openalex.org/I4210090176"],"apc_list":null,"apc_paid":null,"fwci":1.2484,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.82451576,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1353","last_page":"1356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7226719260215759},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6117292642593384},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6032100915908813},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5846588611602783},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4837179481983185},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45546281337738037},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.45408323407173157},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4226223826408386},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3466164469718933},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3354726731777191},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15377399325370789},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07121044397354126}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7226719260215759},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6117292642593384},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6032100915908813},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5846588611602783},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4837179481983185},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45546281337738037},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.45408323407173157},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4226223826408386},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3466164469718933},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3354726731777191},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15377399325370789},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07121044397354126},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457020","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457020","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1833248402","https://openalex.org/W2084730210","https://openalex.org/W2096437225","https://openalex.org/W2097410912","https://openalex.org/W2119826888","https://openalex.org/W2124407221","https://openalex.org/W2149124583","https://openalex.org/W2152042493","https://openalex.org/W3146045665","https://openalex.org/W4240724929","https://openalex.org/W6674503701","https://openalex.org/W6675222231"],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W1991670063","https://openalex.org/W4242565052","https://openalex.org/W2999907514","https://openalex.org/W2362169398","https://openalex.org/W2139353707","https://openalex.org/W4210379803","https://openalex.org/W2134486854"],"abstract_inverted_index":{"Faster-than-at-speed":[0],"testing":[1,28,46],"provides":[2],"an":[3,37],"effective":[4],"way":[5],"for":[6,25,47,103],"detecting":[7],"and":[8,52,91,108],"debugging":[9],"small":[10],"delay":[11,27,45,84],"defects":[12],"in":[13,74,115],"modern":[14],"fabricated":[15],"chips.":[16],"However,":[17],"the":[18,72,75,83,89,100,116,125],"use":[19],"of":[20],"external":[21],"automatic":[22],"test":[23,56,60,76,106,117],"equipment":[24],"faster-than-at-speed":[26,44],"could":[29],"be":[30,68,113],"costly.":[31],"In":[32],"this":[33],"paper,":[34],"we":[35],"present":[36],"on-chip":[38],"clock":[39,61,93,109],"generation":[40,94],"scheme":[41],"which":[42,78],"facilitates":[43],"both":[48],"launch":[49,53,90],"on":[50,54],"capture":[51,92],"shift":[55],"frameworks.":[57],"The":[58],"required":[59],"frequency":[62],"with":[63],"a":[64],"high":[65],"resolution":[66],"can":[67,111],"obtained":[69],"by":[70],"specifying":[71],"information":[73,102],"patterns,":[77],"is":[79],"then":[80],"shifted":[81],"into":[82],"control":[85,101],"stages":[86],"to":[87,123],"configure":[88],"circuit":[95],"(LCCG)":[96],"embedded":[97,114],"on-chip.":[98],"Similarly,":[99],"selecting":[104],"various":[105],"frameworks":[107],"signals":[110],"also":[112],"patterns.":[118],"Experimental":[119],"results":[120],"are":[121],"presented":[122],"validate":[124],"proposed":[126],"scheme.":[127]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
