{"id":"https://openalex.org/W3144226148","doi":"https://doi.org/10.1109/date.2010.5456997","title":"BISD: Scan-based Built-In self-diagnosis","display_name":"BISD: Scan-based Built-In self-diagnosis","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3144226148","doi":"https://doi.org/10.1109/date.2010.5456997","mag":"3144226148"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5456997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075785032","display_name":"Melanie Elm","orcid":null},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Melanie Elm","raw_affiliation_strings":["Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008775226","display_name":"Hans-Joachim Wunderlich","orcid":"https://orcid.org/0000-0003-4536-8290"},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hans-Joachim Wunderlich","raw_affiliation_strings":["Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5075785032"],"corresponding_institution_ids":["https://openalex.org/I100066346"],"apc_list":null,"apc_paid":null,"fwci":1.2519,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82436011,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1243","last_page":"1248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9751999974250793,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.7832974195480347},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7391119599342346},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6800975203514099},{"id":"https://openalex.org/keywords/signature","display_name":"Signature (topology)","score":0.6469966173171997},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5930756330490112},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.552435040473938},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5488911867141724},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.4497043788433075},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.44741928577423096},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4354276657104492},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42913171648979187},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34635430574417114},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34332388639450073},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.32131630182266235},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1429995596408844}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.7832974195480347},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7391119599342346},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6800975203514099},{"id":"https://openalex.org/C2779696439","wikidata":"https://www.wikidata.org/wiki/Q7512811","display_name":"Signature (topology)","level":2,"score":0.6469966173171997},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5930756330490112},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.552435040473938},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5488911867141724},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.4497043788433075},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.44741928577423096},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4354276657104492},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42913171648979187},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34635430574417114},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34332388639450073},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32131630182266235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1429995596408844},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5456997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W100035992","https://openalex.org/W1976062726","https://openalex.org/W1989910051","https://openalex.org/W2021463588","https://openalex.org/W2096366760","https://openalex.org/W2102404182","https://openalex.org/W2106057872","https://openalex.org/W2106772577","https://openalex.org/W2114204923","https://openalex.org/W2116598791","https://openalex.org/W2123887307","https://openalex.org/W2124629389","https://openalex.org/W2127346720","https://openalex.org/W2128426877","https://openalex.org/W2133447618","https://openalex.org/W2137702935","https://openalex.org/W2138530143","https://openalex.org/W2144033909","https://openalex.org/W2149494050","https://openalex.org/W2152489029","https://openalex.org/W2153336129","https://openalex.org/W2155829270","https://openalex.org/W2162765851","https://openalex.org/W2165030600","https://openalex.org/W2169280266","https://openalex.org/W2171837466","https://openalex.org/W3141551298","https://openalex.org/W4230343699","https://openalex.org/W4233158255","https://openalex.org/W4239921811","https://openalex.org/W4246972245","https://openalex.org/W4249806673","https://openalex.org/W4255277216","https://openalex.org/W4255322115","https://openalex.org/W4256404229","https://openalex.org/W6604055980","https://openalex.org/W6677079873","https://openalex.org/W6681008240","https://openalex.org/W6681931124","https://openalex.org/W6684237731"],"related_works":["https://openalex.org/W2989159162","https://openalex.org/W2153201966","https://openalex.org/W2122754719","https://openalex.org/W2124030650","https://openalex.org/W2115073733","https://openalex.org/W2102771100","https://openalex.org/W2146381271","https://openalex.org/W2139513292","https://openalex.org/W1982569681","https://openalex.org/W2165948443"],"abstract_inverted_index":{"Built-In":[0],"Self-Test":[1],"(BIST)":[2],"is":[3,86,115,120,126,165],"less":[4],"often":[5],"applied":[6],"to":[7,11,15,29],"random":[8],"logic":[9],"than":[10],"embedded":[12],"memories":[13],"due":[14],"the":[16,40,48,68,84,94,156,162,171,175],"following":[17],"reasons:":[18],"Firstly,":[19],"for":[20,67,77,93,122,183],"a":[21,60,74,123,137,140,146],"satisfiable":[22],"fault":[23],"coverage":[24],"it":[25],"may":[26],"be":[27,180],"necessary":[28],"apply":[30],"additional":[31,36,157],"deterministic":[32],"patterns,":[33],"which":[34,92,119],"cause":[35],"hardware":[37,107,138,158],"costs.":[38],"Secondly,":[39],"BIST-signature":[41],"reveals":[42],"only":[43],"poor":[44],"diagnostic":[45,177],"information.":[46],"Recently,":[47],"first":[49,95],"issue":[50],"has":[51],"been":[52],"addressed":[53],"successfully.":[54],"The":[55,71,81,109,133],"paper":[56,72],"at":[57],"hand":[58],"proposes":[59],"viable,":[61],"effective":[62],"and":[63,145,174],"cost":[64],"efficient":[65],"solution":[66],"second":[69],"problem.":[70],"presents":[73],"new":[75],"method":[76,85,135,164],"Built-in":[78],"Self-Diagnosis":[79],"(BISD).":[80],"core":[82],"of":[83,102,112,170],"an":[87,98],"extreme":[88],"response":[89],"compaction":[90],"architecture,":[91],"time":[96],"enables":[97],"autonomous":[99],"on-chip":[100],"evaluation":[101],"test":[103,131,141],"responses":[104],"with":[105,151],"negligible":[106],"overhead.":[108],"key":[110],"advantage":[111],"this":[113],"architecture":[114],"that":[116,155],"all":[117],"data,":[118],"relevant":[121],"subsequent":[124],"diagnosis,":[125],"gathered":[127],"during":[128],"just":[129],"one":[130],"session.":[132],"BISD":[134,163],"comprises":[136],"scheme,":[139],"pattern":[142],"generation":[143],"approach":[144],"diagnosis":[147],"algorithm.":[148],"Experiments":[149],"conducted":[150],"industrial":[152],"designs":[153],"substantiate":[154],"overhead":[159],"introduced":[160],"by":[161],"on":[166],"average":[167],"about":[168],"15%":[169],"BIST":[172],"area,":[173],"same":[176],"resolution":[178],"can":[179],"obtained":[181],"as":[182],"external":[184],"testing.":[185]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}