{"id":"https://openalex.org/W4235685886","doi":"https://doi.org/10.1109/date.2010.5456979","title":"General behavioral thermal modeling and characterization for multi-core microprocessor design","display_name":"General behavioral thermal modeling and characterization for multi-core microprocessor design","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4235685886","doi":"https://doi.org/10.1109/date.2010.5456979"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5456979","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456979","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072393373","display_name":"Thom Jefferson A. Eguia","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Thom J A Eguia","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058844682","display_name":"Sheldon X.-D. Tan","orcid":"https://orcid.org/0000-0003-2119-6869"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheldon X.-D Tan","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008663892","display_name":"Ruijing Shen","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ruijing Shen","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000277501","display_name":"Eduardo H. Pacheco","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eduardo H Pacheco","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108090154","display_name":"Murli Tirumala","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Murli Tirumala","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5072393373"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":1.4432,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.84726616,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1136","last_page":"1141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overfitting","display_name":"Overfitting","score":0.9269167184829712},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6981632709503174},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5823597311973572},{"id":"https://openalex.org/keywords/subspace-topology","display_name":"Subspace topology","score":0.4918079674243927},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3240680694580078},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.29443347454071045},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.19436615705490112},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.10226833820343018}],"concepts":[{"id":"https://openalex.org/C22019652","wikidata":"https://www.wikidata.org/wiki/Q331309","display_name":"Overfitting","level":3,"score":0.9269167184829712},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6981632709503174},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5823597311973572},{"id":"https://openalex.org/C32834561","wikidata":"https://www.wikidata.org/wiki/Q660730","display_name":"Subspace topology","level":2,"score":0.4918079674243927},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3240680694580078},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.29443347454071045},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.19436615705490112},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.10226833820343018}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5456979","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456979","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W65564217","https://openalex.org/W1520252399","https://openalex.org/W1585009072","https://openalex.org/W2098228187","https://openalex.org/W2105334538","https://openalex.org/W2110090002","https://openalex.org/W2120368896","https://openalex.org/W2130212796","https://openalex.org/W2133804388","https://openalex.org/W2138616126","https://openalex.org/W2154857344","https://openalex.org/W2527081555","https://openalex.org/W6602628681","https://openalex.org/W6675733323"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W4362597605","https://openalex.org/W1574414179","https://openalex.org/W4297676672","https://openalex.org/W3009056573","https://openalex.org/W2922073769","https://openalex.org/W4281702477","https://openalex.org/W2490526372","https://openalex.org/W4376166922"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,104,116,159],"new":[4,25,99,142],"architecture-level":[5],"thermal":[6,13,29,37,52,111],"modeling":[7,53,82,185],"method":[8,57,100,107,143],"to":[9,108,149,182],"address":[10],"the":[11,28,33,42,55,60,73,81,110,134,138,141,170,175],"emerging":[12],"related":[14],"analysis":[15],"and":[16,38,68,86,91,153,187],"optimization":[17],"problem":[18],"for":[19,45,94],"high-performance":[20],"multi-core":[21,46],"microprocessor":[22,162],"design.":[23],"The":[24,98],"approach":[26,78],"builds":[27],"behavioral":[30,51,61],"models":[31,62],"from":[32,63,122],"measured":[34,96],"or":[35],"simulated":[36],"power":[39,67],"information":[40],"at":[41],"architecture":[43],"level":[44],"processors.":[47],"Compared":[48],"with":[49],"existing":[50,171],"algorithms,":[54],"proposed":[56,176],"can":[58,79],"build":[59,109],"given":[64],"arbitrary":[65],"transient":[66],"temperature":[69],"waveforms":[70],"used":[71],"as":[72],"training":[74],"data.":[75,97],"Such":[76],"an":[77,145],"make":[80],"process":[83],"much":[84],"easier":[85],"less":[87],"restrictive":[88],"than":[89,169],"before,":[90],"more":[92,167],"amenable":[93],"practical":[95],"is":[101,166,180],"based":[102],"on":[103,158],"subspace":[105,139],"identification":[106],"models,":[112],"which":[113,123],"first":[114],"generates":[115],"Hankel":[117],"matrix":[118],"of":[119,137],"Markov":[120],"parameters,":[121],"state":[124],"matrices":[125],"are":[126],"obtained":[127],"through":[128],"minimum":[129],"square":[130],"optimization.":[131],"To":[132],"overcome":[133],"overfitting":[135,146,177],"problems":[136],"method,":[140],"employs":[144],"mitigation":[147,178],"technique":[148,179],"improve":[150,184],"model":[151],"accuracy":[152,186],"predictive":[154],"ability.":[155],"Experimental":[156],"results":[157],"real":[160],"quad-core":[161],"show":[163],"that":[164],"ThermSID":[165],"accurate":[168],"ThermPOF":[172],"method.":[173],"Furthermore,":[174],"shown":[181],"significantly":[183],"predictability.":[188]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
