{"id":"https://openalex.org/W3152096162","doi":"https://doi.org/10.1109/date.2010.5456953","title":"Throughput modeling to evaluate process merging transformations in polyhedral process networks","display_name":"Throughput modeling to evaluate process merging transformations in polyhedral process networks","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3152096162","doi":"https://doi.org/10.1109/date.2010.5456953","mag":"3152096162"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5456953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030570166","display_name":"Sybren L. Meijer","orcid":"https://orcid.org/0000-0002-6953-2406"},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"S Meijer","raw_affiliation_strings":["Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands"],"affiliations":[{"raw_affiliation_string":"Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067545421","display_name":"Hristo Nikolov","orcid":"https://orcid.org/0000-0001-5764-1499"},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"H Nikolov","raw_affiliation_strings":["Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands"],"affiliations":[{"raw_affiliation_string":"Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024603788","display_name":"Todor Stefanov","orcid":"https://orcid.org/0000-0001-6006-9366"},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"T Stefanov","raw_affiliation_strings":["Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands"],"affiliations":[{"raw_affiliation_string":"Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030570166"],"corresponding_institution_ids":["https://openalex.org/I121797337"],"apc_list":null,"apc_paid":null,"fwci":2.0031,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.88290674,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"747","last_page":"752"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8173074722290039},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.8040512800216675},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.7181884050369263},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6884733438491821},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6064201593399048},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5647017359733582},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.5013210773468018},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.500356912612915},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4635407626628876},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.44057410955429077},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43613487482070923},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.42662182450294495},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40472960472106934},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.3914391100406647},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14042282104492188},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08544310927391052}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8173074722290039},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.8040512800216675},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.7181884050369263},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6884733438491821},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6064201593399048},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5647017359733582},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.5013210773468018},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.500356912612915},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4635407626628876},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.44057410955429077},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43613487482070923},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.42662182450294495},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40472960472106934},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3914391100406647},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14042282104492188},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08544310927391052},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5456953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5456953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1974386461","https://openalex.org/W2028369847","https://openalex.org/W2108662993","https://openalex.org/W2113172369","https://openalex.org/W2114758860","https://openalex.org/W2120411167","https://openalex.org/W2125658777","https://openalex.org/W2160737725","https://openalex.org/W2575267709","https://openalex.org/W3147122452","https://openalex.org/W4245669254","https://openalex.org/W6643789780"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2170552397","https://openalex.org/W2540393334","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2085828379","https://openalex.org/W2271847574","https://openalex.org/W2017144313"],"abstract_inverted_index":{"We":[0,49,81],"use":[1],"the":[2,25,39,56,78,88],"polyhedral":[3],"process":[4,40],"network":[5,31],"(PPN)":[6],"model":[7],"of":[8,27,59],"computation":[9],"to":[10,23,33,46,54,63,77],"program":[11],"embedded":[12],"Multi-Processor":[13],"Systems":[14],"on":[15,87,92],"Chip":[16],"(MPSoCs)":[17],"platforms.":[18],"If":[19],"a":[20,30,51,65,70,93],"designer":[21],"wants":[22],"reduce":[24],"number":[26],"processes":[28],"in":[29,61],"due":[32],"resource":[34],"constraints,":[35],"for":[36,84],"example,":[37],"then":[38],"merging":[41,66],"transformation":[42],"can":[43],"be":[44],"used":[45],"achieve":[47],"this.":[48],"present":[50],"compile-time":[52],"approach":[53],"evaluate":[55],"system":[57,71],"throughput":[58,72],"PPNs":[60],"order":[62],"select":[64],"candidate":[67],"which":[68],"gives":[69],"as":[73,75],"close":[74],"possible":[76],"original":[79],"PPN.":[80],"show":[82],"results":[83],"two":[85],"experiments":[86],"ESPAM":[89],"platform":[90],"prototyped":[91],"Xilinx":[94],"Virtex":[95],"2":[96],"Pro":[97],"FPGA.":[98]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}