{"id":"https://openalex.org/W3143527577","doi":"https://doi.org/10.1109/date.2009.5090903","title":"SC-DEVS: An efficient SystemC extension for the DEVS model of computation","display_name":"SC-DEVS: An efficient SystemC extension for the DEVS model of computation","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3143527577","doi":"https://doi.org/10.1109/date.2009.5090903","mag":"3143527577"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090903","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090903","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006299407","display_name":"Felix Madlener","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"F. Madlener","raw_affiliation_strings":["Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014313362","display_name":"H. Gregor Molter","orcid":"https://orcid.org/0000-0002-6896-1591"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"H.G. Molter","raw_affiliation_strings":["Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109870848","display_name":"Sorin A. Huss","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S.A. Huss","raw_affiliation_strings":["Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits and Systems Laboratory, Technische Universit\u00e4t Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":0.7316,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.71406127,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1518","last_page":"1523"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9871730804443359},{"id":"https://openalex.org/keywords/devs","display_name":"DEVS","score":0.9636019468307495},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.830781102180481},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.6602632999420166},{"id":"https://openalex.org/keywords/extension","display_name":"Extension (predicate logic)","score":0.6031014323234558},{"id":"https://openalex.org/keywords/discrete-event-simulation","display_name":"Discrete event simulation","score":0.5751665234565735},{"id":"https://openalex.org/keywords/model-of-computation","display_name":"Model of computation","score":0.569672167301178},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5314815044403076},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.5021719932556152},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.4603222906589508},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4332968592643738},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38842660188674927},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36844563484191895},{"id":"https://openalex.org/keywords/modeling-and-simulation","display_name":"Modeling and simulation","score":0.2542785406112671},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2465459704399109},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.10850265622138977}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9871730804443359},{"id":"https://openalex.org/C68757728","wikidata":"https://www.wikidata.org/wiki/Q911082","display_name":"DEVS","level":3,"score":0.9636019468307495},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.830781102180481},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.6602632999420166},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.6031014323234558},{"id":"https://openalex.org/C147203929","wikidata":"https://www.wikidata.org/wiki/Q574814","display_name":"Discrete event simulation","level":2,"score":0.5751665234565735},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.569672167301178},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5314815044403076},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.5021719932556152},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.4603222906589508},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4332968592643738},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38842660188674927},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36844563484191895},{"id":"https://openalex.org/C167343916","wikidata":"https://www.wikidata.org/wiki/Q6888384","display_name":"Modeling and simulation","level":2,"score":0.2542785406112671},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2465459704399109},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.10850265622138977},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090903","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090903","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1490832609","https://openalex.org/W1501867347","https://openalex.org/W1964617631","https://openalex.org/W1985142635","https://openalex.org/W2048677734","https://openalex.org/W2074100014","https://openalex.org/W2126270278","https://openalex.org/W2138803629","https://openalex.org/W2140460152","https://openalex.org/W2334494444","https://openalex.org/W6662899192"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2266880325","https://openalex.org/W2097331811","https://openalex.org/W2112120387","https://openalex.org/W1981924702","https://openalex.org/W2531335688","https://openalex.org/W2168814075","https://openalex.org/W1985142635"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,70,79],"systematic":[4],"approach":[5,103],"to":[6,44,53,82],"integrate":[7],"the":[8,27,83,98],"Discrete":[9],"Event":[10],"Specified":[11],"System":[12],"(DEVS)":[13],"methodology":[14],"into":[15],"SystemC.":[16],"It":[17],"thus":[18],"combines":[19],"Model":[20],"of":[21,29,36],"Computation":[22],"(MoC)":[23],"specific":[24],"properties":[25],"and":[26,48],"features":[28],"an":[30,93],"advanced":[31],"SystemC":[32,46,71,84,99],"environment.":[33,72],"The":[34,73,87],"execution":[35],"abstract":[37,63],"system":[38,58],"level":[39,59],"DEVS":[40,55,88],"models":[41,47,60,89],"is":[42,49,76],"comparable":[43],"pure":[45],"significantly":[50],"faster":[51],"compared":[52],"other":[54,109],"environments.":[56],"Thus,":[57],"based":[61],"on":[62,92],"MoCs":[64],"may":[65,104],"easily":[66],"be":[67,105],"executed":[68],"in":[69],"proposed":[74],"integration":[75],"realized":[77],"as":[78],"non-introspective":[80],"extension":[81],"2.2":[85],"kernel.":[86,101],"are":[90],"implemented":[91],"additional":[94],"software":[95],"layer":[96],"above":[97],"simulation":[100],"Our":[102],"used":[106],"simultaneously":[107],"with":[108],"layered":[110],"extensions,":[111],"e.g.,":[112],"SystemC-AMS":[113],"or":[114],"TLM.":[115]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
