{"id":"https://openalex.org/W3149594966","doi":"https://doi.org/10.1109/date.2009.5090845","title":"Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design","display_name":"Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3149594966","doi":"https://doi.org/10.1109/date.2009.5090845","mag":"3149594966"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090845","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113532435","display_name":"Steven F. Perry","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094575","display_name":"Altera (United Kingdom)","ror":"https://ror.org/00m96gg93","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210094575"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"S. Perry","raw_affiliation_strings":["European Technology Centre, Altera Corporation, High Wycombe, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"European Technology Centre, Altera Corporation, High Wycombe, UK","institution_ids":["https://openalex.org/I4210094575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113532435"],"corresponding_institution_ids":["https://openalex.org/I4210094575"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1202","last_page":"1207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9785000085830688,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.8759702444076538},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7722486257553101},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.744927167892456},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6927574872970581},{"id":"https://openalex.org/keywords/high-level-design","display_name":"High-level design","score":0.655790388584137},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6044497489929199},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5459635853767395},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.5326385498046875},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.5227630138397217},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5027856826782227},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.48104527592658997},{"id":"https://openalex.org/keywords/design-cycle","display_name":"Design cycle","score":0.4708171486854553},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4437345862388611},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44104331731796265},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4183931052684784},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3523654341697693},{"id":"https://openalex.org/keywords/iterative-design","display_name":"Iterative design","score":0.2949710190296173},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2914615869522095},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.12269994616508484},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.11635398864746094},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10433241724967957},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0975838303565979},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.08926105499267578}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.8759702444076538},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7722486257553101},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.744927167892456},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6927574872970581},{"id":"https://openalex.org/C78246475","wikidata":"https://www.wikidata.org/wiki/Q5754546","display_name":"High-level design","level":4,"score":0.655790388584137},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6044497489929199},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5459635853767395},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.5326385498046875},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.5227630138397217},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5027856826782227},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.48104527592658997},{"id":"https://openalex.org/C2982740150","wikidata":"https://www.wikidata.org/wiki/Q5249230","display_name":"Design cycle","level":2,"score":0.4708171486854553},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4437345862388611},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44104331731796265},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4183931052684784},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3523654341697693},{"id":"https://openalex.org/C106246047","wikidata":"https://www.wikidata.org/wiki/Q4928435","display_name":"Iterative design","level":3,"score":0.2949710190296173},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2914615869522095},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.12269994616508484},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.11635398864746094},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10433241724967957},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0975838303565979},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.08926105499267578},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090845","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2104869032","https://openalex.org/W2120060202","https://openalex.org/W2134060873"],"related_works":["https://openalex.org/W2105118350","https://openalex.org/W2140420993","https://openalex.org/W2144666235","https://openalex.org/W1491766829","https://openalex.org/W2126751824","https://openalex.org/W2128393696","https://openalex.org/W4240364834","https://openalex.org/W1986165211","https://openalex.org/W2117468945","https://openalex.org/W2576551918"],"abstract_inverted_index":{"Model":[0],"Based":[1],"Design":[2],"tools":[3,40],"based":[4],"around":[5],"Simulink":[6],"from":[7,150],"The":[8],"MathWorks":[9],"are":[10,131,143,168],"a":[11,43,91,96,108,113,170,186],"popular":[12],"technology":[13,156],"for":[14,21,107],"the":[15,26,53,62,140,146,155,160,163,174],"creation":[16],"of":[17,28,36,45,52,86,99,126,136,162],"streaming":[18],"DSP":[19,147],"designs":[20,119],"FPGAs,":[22],"since":[23,61],"they":[24],"offer":[25],"promise":[27],"rapid":[29],"design":[30,75,94,109,115,189],"exploration":[31],"through":[32],"immediate":[33],"quantitative":[34],"feedback":[35],"algorithm":[37],"performance.":[38],"Current":[39],"typically":[41],"use":[42],"library":[44],"components":[46,105],"that":[47,83],"reflect":[48],"an":[49],"explicit":[50],"representation":[51,178],"underlying":[54],"FPGA":[55,137],"device":[56],"features.":[57],"This":[58,80,101],"is":[59,64],"undesirable":[60],"designer":[63],"forced":[65],"to":[66,73,128],"mix":[67],"implementation":[68],"and":[69,71,77,120,184],"architecture,":[70],"leads":[72],"long":[74],"cycles":[76],"non-portable":[78],"results.":[79],"paper":[81,153],"shows":[82],"introducing":[84],"techniques":[85],"high":[87],"level":[88,98,176],"synthesis":[89],"allows":[90],"more":[92,117],"elegant":[93],"at":[95],"higher":[97],"abstraction.":[100],"results":[102],"in":[103,145],"fewer":[104,121],"needed":[106],"which":[110],"translates":[111],"into":[112],"faster":[114],"cycle,":[116],"portable":[118],"defects.":[122],"Pushbutton":[123],"clock":[124],"frequencies":[125],"up":[127],"500":[129],"MHz":[130],"achieved":[132],"without":[133],"detailed":[134],"knowledge":[135],"architectures.":[138],"Although":[139],"capabilities":[141],"described":[142],"embodied":[144],"Builder":[148],"tool":[149,190],"Altera,":[151],"this":[152],"describes":[154],"involved":[157],"rather":[158],"than":[159],"details":[161],"tools.":[164],"Four":[165],"major":[166],"technologies":[167],"described:":[169],"latency-insensitive":[171],"system":[172],"representation,":[173],"module":[175],"internal":[177],"with":[179],"associated":[180],"transformations,":[181],"hardware":[182],"retiming,":[183],"lastly":[185],"FIR":[187],"filter":[188],"layered":[191],"on":[192],"top.":[193]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}
