{"id":"https://openalex.org/W3139803046","doi":"https://doi.org/10.1109/date.2009.5090793","title":"Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip","display_name":"Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3139803046","doi":"https://doi.org/10.1109/date.2009.5090793","mag":"3139803046"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090793","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090793","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010034275","display_name":"Francesco Paterna","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Francesco Paterna","raw_affiliation_strings":["DEIS - University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS - University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS - University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS - University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017681035","display_name":"Francesco Papariello","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Papariello","raw_affiliation_strings":["DAUIN Politecnico di Torino, Torino, Italy","ST Microelectromcs, Agrate, Italy"],"affiliations":[{"raw_affiliation_string":"DAUIN Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"ST Microelectromcs, Agrate, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047102959","display_name":"Giuseppe Desoli","orcid":"https://orcid.org/0000-0002-3901-0770"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Giuseppe Desoli","raw_affiliation_strings":["ST Microelectromcs, Agrate, Italy"],"affiliations":[{"raw_affiliation_string":"ST Microelectromcs, Agrate, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031653904","display_name":"Andrea Acquaviva","orcid":"https://orcid.org/0000-0002-7323-759X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Acquaviva","raw_affiliation_strings":["DAVIN - Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"DAVIN - Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Olivieri","raw_affiliation_strings":["DIE - Universit \u201cLa Sapienza\u201d di Roma, Roma, Italy","DIE - Universit \"La Sapienza\" di Roma, Roma, Italy"],"affiliations":[{"raw_affiliation_string":"DIE - Universit \u201cLa Sapienza\u201d di Roma, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"DIE - Universit \"La Sapienza\" di Roma, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5010034275"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":0.7915,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.76447953,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"906","last_page":"909"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9473951458930969},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.8039261102676392},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7419025301933289},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.6226887702941895},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5997971892356873},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.5408769845962524},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5294520258903503},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5122979879379272},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4356876611709595},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3754756450653076},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.333585262298584},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18502792716026306}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9473951458930969},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.8039261102676392},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7419025301933289},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.6226887702941895},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5997971892356873},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.5408769845962524},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5294520258903503},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5122979879379272},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4356876611709595},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3754756450653076},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.333585262298584},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18502792716026306}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090793","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090793","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W147650083","https://openalex.org/W2008603183","https://openalex.org/W2170509664","https://openalex.org/W2789221923","https://openalex.org/W6605987033"],"related_works":["https://openalex.org/W4281711577","https://openalex.org/W2106200299","https://openalex.org/W2326041751","https://openalex.org/W2178653557","https://openalex.org/W2540211551","https://openalex.org/W2994908368","https://openalex.org/W1975982080","https://openalex.org/W1976012348","https://openalex.org/W2614713859","https://openalex.org/W2002682434"],"abstract_inverted_index":{"In":[0,28],"deep":[1],"submicron":[2],"designs":[3],"of":[4,24,41,50,61,85,95],"MultiProcessor":[5],"Systems-on-Chip":[6],"(MPSoC)":[7],"architectures,":[8],"uncompensated":[9],"within-die":[10],"process":[11],"variations":[12],"and":[13,22,43,100],"aging":[14],"effects":[15],"will":[16],"lead":[17],"to":[18,67],"an":[19,33],"increasing":[20],"uncertainty":[21],"unbalancing":[23],"expected":[25],"core":[26,46,51],"lifetimes.":[27],"this":[29],"paper":[30],"we":[31],"present":[32],"adaptive":[34],"workload":[35],"allocation":[36],"strategy":[37],"for":[38,91],"run-time":[39],"compensation":[40],"variations-":[42],"aging-induced":[44],"unbalanced":[45],"lifetimes":[47],"by":[48],"means":[49],"activity":[52],"duty":[53],"cycling.":[54],"The":[55],"proposed":[56],"techniques":[57],"regulates":[58],"the":[59,69],"percentage":[60],"idle":[62],"time":[63],"on":[64,81],"short-expected-life":[65],"cores":[66],"meet":[68],"platform":[70,90],"lifetime":[71],"target":[72],"with":[73],"minimum":[74],"performance":[75],"degradation.":[76],"Experiments":[77],"have":[78],"been":[79],"conducted":[80],"a":[82,86,96],"multiprocessor":[83],"simulator":[84],"next-generation":[87],"industrial":[88],"MPSoC":[89],"multimedia":[92],"applications":[93],"made":[94],"general":[97],"purpose":[98],"processor":[99],"programmable":[101],"accelerators.":[102]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}