{"id":"https://openalex.org/W4248817287","doi":"https://doi.org/10.1109/date.2009.5090789","title":"Automated synthesis of streaming C applications to process networks in hardware","display_name":"Automated synthesis of streaming C applications to process networks in hardware","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W4248817287","doi":"https://doi.org/10.1109/date.2009.5090789"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079486968","display_name":"Sven van Haastregt","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"S. van Haastregt","raw_affiliation_strings":["LIACS, Leiden University, Leiden, Netherlands"],"affiliations":[{"raw_affiliation_string":"LIACS, Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036728330","display_name":"B. Kienhuis","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"B. Kienhuis","raw_affiliation_strings":["LIACS, Leiden University, Leiden, Netherlands"],"affiliations":[{"raw_affiliation_string":"LIACS, Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5079486968"],"corresponding_institution_ids":["https://openalex.org/I121797337"],"apc_list":null,"apc_paid":null,"fwci":1.5829,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.85397139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"890","last_page":"893"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8406778573989868},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.782977819442749},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5408689379692078},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5364473462104797},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5290588140487671},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5159500241279602},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5146751999855042},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4109959006309509},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38421764969825745},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36698445677757263},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23700398206710815}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8406778573989868},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.782977819442749},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5408689379692078},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5364473462104797},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5290588140487671},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5159500241279602},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5146751999855042},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4109959006309509},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38421764969825745},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36698445677757263},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23700398206710815},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1550689936","https://openalex.org/W1974386461","https://openalex.org/W2036673855","https://openalex.org/W2103581911","https://openalex.org/W2108662993","https://openalex.org/W2114758860","https://openalex.org/W4245669254"],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2160632767","https://openalex.org/W1608572506","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W2000188956","https://openalex.org/W1973862904","https://openalex.org/W181593118"],"abstract_inverted_index":{"The":[0,55],"demand":[1],"for":[2,133],"embedded":[3],"computing":[4,15],"power":[5],"is":[6,28],"continuously":[7],"increasing":[8],"and":[9,63,136],"FPGAs":[10,50,117],"are":[11],"becoming":[12],"very":[13],"interesting":[14],"platforms,":[16],"as":[17],"they":[18],"provide":[19],"huge":[20],"amounts":[21],"of":[22,58,61,112,125],"customizable":[23],"parallelism.":[24],"However,":[25],"programming":[26],"them":[27],"challenging,":[29],"let":[30],"alone":[31],"from":[32,51,101,118],"a":[33,59,69,119,126],"high":[34,96],"level":[35,97],"language.":[36],"In":[37,66,81,104],"[1],":[38],"the":[39,73,89,94,109,134],"ESPAM":[40,90],"methodology":[41,91],"was":[42,71],"already":[43],"presented":[44],"to":[45,77],"quickly":[46],"obtain":[47],"realizations":[48],"on":[49,88,116],"sequential":[52,121],"C":[53,122],"code.":[54],"realization":[56],"consists":[57],"network":[60],"processors":[62],"IP":[64,74],"cores.":[65],"this":[67,82,105],"approach,":[68],"problem":[70],"that":[72],"cores":[75],"had":[76],"be":[78],"provided":[79],"manually.":[80],"paper,":[83],"we":[84,107],"present":[85],"an":[86],"extension":[87],"by":[92],"incorporating":[93],"industrial":[95],"synthesis":[98],"tool":[99],"PICO":[100],"Synfora":[102],"Inc.":[103],"way,":[106],"realize":[108],"automated":[110],"generation":[111],"efficient":[113],"hardware":[114],"implementations":[115],"single":[120],"input":[123],"specification":[124],"streaming":[127],"application.":[128],"We":[129],"demonstrate":[130],"our":[131],"approach":[132],"Sobel":[135],"QR":[137],"applications.":[138]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}