{"id":"https://openalex.org/W4233186633","doi":"https://doi.org/10.1109/date.2009.5090729","title":"SecBus: Operating System controlled hierarchical page-based memory bus protection","display_name":"SecBus: Operating System controlled hierarchical page-based memory bus protection","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W4233186633","doi":"https://doi.org/10.1109/date.2009.5090729"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065769873","display_name":"Li-Feng Su","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"id":"https://openalex.org/I4210106035","display_name":"STMicroelectronics (United States)","ror":"https://ror.org/01f8c3y78","country_code":"US","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210106035"]}],"countries":["FR","US"],"is_corresponding":true,"raw_author_name":"Lifeng Su","raw_affiliation_strings":["STMicroelectronics, Rousset, France","STMicroelectronics [Rousset]"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Rousset, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"STMicroelectronics [Rousset]","institution_ids":["https://openalex.org/I4210106035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029837083","display_name":"S. Courcambeck","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106035","display_name":"STMicroelectronics (United States)","ror":"https://ror.org/01f8c3y78","country_code":"US","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210106035"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"S. Courcambeck","raw_affiliation_strings":["STMicroelectronics, Rousset, France","STMicroelectronics [Rousset]"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Rousset, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"STMicroelectronics [Rousset]","institution_ids":["https://openalex.org/I4210106035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021643185","display_name":"P. Guillemin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106035","display_name":"STMicroelectronics (United States)","ror":"https://ror.org/01f8c3y78","country_code":"US","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210106035"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"P. Guillemin","raw_affiliation_strings":["STMicroelectronics, Rousset, France","STMicroelectronics [Rousset]"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Rousset, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"STMicroelectronics [Rousset]","institution_ids":["https://openalex.org/I4210106035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058008550","display_name":"C. Schwarz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106035","display_name":"STMicroelectronics (United States)","ror":"https://ror.org/01f8c3y78","country_code":"US","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210106035"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"C. Schwarz","raw_affiliation_strings":["STMicroelectronics, Rousset, France","STMicroelectronics [Rousset]"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Rousset, France","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"STMicroelectronics [Rousset]","institution_ids":["https://openalex.org/I4210106035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066041952","display_name":"Renaud Pacalet","orcid":"https://orcid.org/0000-0002-6676-1123"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I205703379","display_name":"Institut Mines-T\u00e9l\u00e9com","ror":"https://ror.org/025vp2923","country_code":"FR","type":"facility","lineage":["https://openalex.org/I205703379"]},{"id":"https://openalex.org/I4210165912","display_name":"Laboratoire Traitement et Communication de l\u2019Information","ror":"https://ror.org/057er4c39","country_code":"FR","type":"facility","lineage":["https://openalex.org/I12356871","https://openalex.org/I205703379","https://openalex.org/I4210145102","https://openalex.org/I4210165912"]},{"id":"https://openalex.org/I12356871","display_name":"T\u00e9l\u00e9com Paris","ror":"https://ror.org/01naq7912","country_code":"FR","type":"education","lineage":["https://openalex.org/I12356871","https://openalex.org/I205703379","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"R. Pacalet","raw_affiliation_strings":["TELECOM ParisTech; CNRS LTCI, Institut TELECOM, Sophia-Antipolis, France","D\u00e9partement Communications & Electronique","Laboratoire Traitement et Communication de l'Information","T\u00e9l\u00e9com ParisTech"],"affiliations":[{"raw_affiliation_string":"TELECOM ParisTech; CNRS LTCI, Institut TELECOM, Sophia-Antipolis, France","institution_ids":["https://openalex.org/I4210165912","https://openalex.org/I205703379","https://openalex.org/I1294671590","https://openalex.org/I12356871"]},{"raw_affiliation_string":"D\u00e9partement Communications & Electronique","institution_ids":[]},{"raw_affiliation_string":"Laboratoire Traitement et Communication de l'Information","institution_ids":["https://openalex.org/I4210165912"]},{"raw_affiliation_string":"T\u00e9l\u00e9com ParisTech","institution_ids":["https://openalex.org/I12356871"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065769873"],"corresponding_institution_ids":["https://openalex.org/I4210104693","https://openalex.org/I4210106035"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.44672002,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"570","last_page":"573"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11614","display_name":"Cloud Data Security Solutions","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.788833498954773},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.7515067458152771},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7042050361633301},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6293598413467407},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.507495105266571},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4876450300216675},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.4795896112918854},{"id":"https://openalex.org/keywords/back-side-bus","display_name":"Back-side bus","score":0.479566752910614},{"id":"https://openalex.org/keywords/control-bus","display_name":"Control bus","score":0.47863832116127014},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4650828242301941},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4586058557033539},{"id":"https://openalex.org/keywords/address-bus","display_name":"Address bus","score":0.45788896083831787},{"id":"https://openalex.org/keywords/confidentiality","display_name":"Confidentiality","score":0.45417237281799316},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4234268367290497},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.42209935188293457},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41827869415283203},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.41730695962905884},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3670125901699066},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.32259851694107056},{"id":"https://openalex.org/keywords/local-bus","display_name":"Local bus","score":0.2639842629432678},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.21537461876869202},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.19000640511512756},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1614307165145874}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.788833498954773},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.7515067458152771},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7042050361633301},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6293598413467407},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.507495105266571},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4876450300216675},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.4795896112918854},{"id":"https://openalex.org/C121013533","wikidata":"https://www.wikidata.org/wiki/Q742323","display_name":"Back-side bus","level":5,"score":0.479566752910614},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.47863832116127014},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4650828242301941},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4586058557033539},{"id":"https://openalex.org/C54714250","wikidata":"https://www.wikidata.org/wiki/Q178048","display_name":"Address bus","level":3,"score":0.45788896083831787},{"id":"https://openalex.org/C71745522","wikidata":"https://www.wikidata.org/wiki/Q2476929","display_name":"Confidentiality","level":2,"score":0.45417237281799316},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4234268367290497},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.42209935188293457},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41827869415283203},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.41730695962905884},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3670125901699066},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.32259851694107056},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.2639842629432678},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.21537461876869202},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.19000640511512756},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1614307165145874},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2009.5090729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-02893203v1","is_oa":false,"landing_page_url":"https://telecom-paris.hal.science/hal-02893203","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09), Apr 2009, Nice, France. pp.570-573, &#x27E8;10.1109/DATE.2009.5090729&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2005725110","https://openalex.org/W2108028555","https://openalex.org/W2134623309","https://openalex.org/W2140972824","https://openalex.org/W2144163129","https://openalex.org/W2160773001","https://openalex.org/W2162034976","https://openalex.org/W2240862428","https://openalex.org/W2428684340","https://openalex.org/W6683496931"],"related_works":["https://openalex.org/W4245683708","https://openalex.org/W4212945793","https://openalex.org/W2781766703","https://openalex.org/W2386568907","https://openalex.org/W2375440962","https://openalex.org/W2166704123","https://openalex.org/W2097792222","https://openalex.org/W1751300046","https://openalex.org/W4233186633","https://openalex.org/W2117332987"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,16,86],"new":[4],"two-levels":[5],"page-based":[6],"memory":[7,27,41,51,90],"bus":[8,38],"protection":[9],"scheme.":[10],"A":[11],"trusted":[12],"Operating":[13],"System":[14],"drives":[15],"hardware":[17,30,82],"cryptographic":[18],"unit":[19,31],"and":[20,39,47,60,74,81,84],"manages":[21],"security":[22,71],"contexts":[23],"for":[24],"each":[25],"protected":[26],"page.":[28],"The":[29,67],"is":[32,76],"located":[33],"between":[34],"the":[35,40,45,56,61,70],"internal":[36],"system":[37],"controller.":[42],"It":[43],"protects":[44],"integrity":[46],"confidentiality":[48],"of":[49,69,89],"selected":[50],"pages.":[52],"For":[53],"better":[54],"acceptability":[55],"processor":[57],"(CPU)":[58],"architecture":[59],"software":[62],"application":[63],"level":[64],"are":[65],"unmodified.":[66],"impact":[68],"on":[72,93],"cost":[73],"performance":[75],"optimized":[77],"by":[78,85],"several":[79],"algorithmic":[80],"techniques":[83],"differentiated":[87],"handling":[88],"pages,":[91],"depending":[92],"their":[94],"characteristics.":[95]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
