{"id":"https://openalex.org/W3147500287","doi":"https://doi.org/10.1109/date.2009.5090665","title":"Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA","display_name":"Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3147500287","doi":"https://doi.org/10.1109/date.2009.5090665","mag":"3147500287"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028905882","display_name":"Tero Arpinen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T. Arpinen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060403555","display_name":"Tuomas Koskinen","orcid":"https://orcid.org/0000-0002-6389-5150"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T. Koskinen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078390067","display_name":"Erno Salminen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"E. Salminen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102937415","display_name":"Timo D. H\u00e4m\u00e4l\u00e4inen","orcid":"https://orcid.org/0000-0002-7867-0800"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T.D. Hamalainen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028871801","display_name":"Marko H\u00e4nnik\u00e4inen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"M. Hannikainen","raw_affiliation_strings":["Department of Computer Systems, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0723,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80535579,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"244","last_page":"249"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8040530681610107},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6812276840209961},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6619616746902466},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5375755429267883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49396830797195435},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.44635283946990967},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.41212528944015503},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19596540927886963}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8040530681610107},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6812276840209961},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6619616746902466},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5375755429267883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49396830797195435},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.44635283946990967},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.41212528944015503},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19596540927886963}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W192742926","https://openalex.org/W2031699358","https://openalex.org/W2140589989","https://openalex.org/W2541785126","https://openalex.org/W4251550447","https://openalex.org/W6607814569"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2784097135","https://openalex.org/W2084925448","https://openalex.org/W3142211975","https://openalex.org/W4312076519","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040"],"abstract_inverted_index":{"IP-XACT":[0,20,57,93],"is":[1,79],"a":[2,67,84],"standard":[3],"for":[4,9,109],"describing":[5],"intellectual":[6],"property":[7],"metadata":[8],"System-on-Chip":[10],"(SoC)":[11],"integration.":[12],"Recently":[13],"researchers":[14],"have":[15],"proposed":[16],"visualizing":[17],"and":[18,27,65,96],"abstracting":[19],"objects":[21],"using":[22,89],"structural":[23],"UML2":[24,54,90],"model":[25],"elements":[26],"diagrams.":[28],"Despite":[29],"the":[30,80,110],"number":[31],"of":[32,56,76,83],"proposals":[33],"at":[34],"conceptual":[35],"level,":[36],"experiences":[37],"on":[38,71,87],"utilizing":[39],"this":[40,77],"representation":[41],"in":[42],"practical":[43],"SoC":[44,69],"development":[45,82],"environments":[46],"are":[47,104],"very":[48],"limited.":[49],"This":[50],"paper":[51,78],"presents":[52],"how":[53],"models":[55],"features":[58],"can":[59],"be":[60],"utilized":[61,111],"to":[62],"efficiently":[63],"design":[64,91,97],"implement":[66],"multiprocessor":[68,85],"prototype":[70],"FPGA.":[72],"The":[73],"main":[74],"contribution":[75],"experimental":[81],"platform":[86],"FPGA":[88],"capture,":[92],"compatible":[94],"components,":[95],"automation":[98],"tools.":[99],"In":[100],"addition,":[101],"modeling":[102],"concepts":[103],"improved":[105],"from":[106],"earlier":[107],"work":[108],"integration":[112],"methodology.":[113]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}