{"id":"https://openalex.org/W3145349486","doi":"https://doi.org/10.1109/date.2009.5090645","title":"A formal approach to design space exploration of protocol converters","display_name":"A formal approach to design space exploration of protocol converters","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3145349486","doi":"https://doi.org/10.1109/date.2009.5090645","mag":"3145349486"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090645","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083055644","display_name":"Karin Avnit","orcid":"https://orcid.org/0000-0001-8126-0768"},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"K. Avnit","raw_affiliation_strings":["School of Computer Science and Engineering, University of New South Wales, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, University of New South Wales, Sydney, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055952724","display_name":"Arcot Sowmya","orcid":"https://orcid.org/0000-0001-9236-5063"},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"A. Sowmya","raw_affiliation_strings":["School of Computer Science and Engineering, University of New South Wales, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, University of New South Wales, Sydney, Australia","institution_ids":["https://openalex.org/I31746571"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083055644"],"corresponding_institution_ids":["https://openalex.org/I31746571"],"apc_list":null,"apc_paid":null,"fwci":1.8404,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.87090308,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.8242114186286926},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6750836372375488},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.606679379940033},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5629542469978333},{"id":"https://openalex.org/keywords/nondeterministic-algorithm","display_name":"Nondeterministic algorithm","score":0.5491299629211426},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42893242835998535},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4267120957374573},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42553064227104187},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.41995179653167725},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.391959011554718},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.18997547030448914},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1437007188796997},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13887551426887512},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12381070852279663},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10384368896484375}],"concepts":[{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.8242114186286926},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6750836372375488},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.606679379940033},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5629542469978333},{"id":"https://openalex.org/C176181172","wikidata":"https://www.wikidata.org/wiki/Q3490301","display_name":"Nondeterministic algorithm","level":2,"score":0.5491299629211426},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42893242835998535},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4267120957374573},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42553064227104187},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.41995179653167725},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.391959011554718},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.18997547030448914},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1437007188796997},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13887551426887512},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12381070852279663},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10384368896484375},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090645","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320290","display_name":"University of Oxford","ror":"https://ror.org/052gg0110"},{"id":"https://openalex.org/F4320320965","display_name":"University of New South Wales","ror":"https://ror.org/03r8z3t63"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1988661459","https://openalex.org/W2047314385","https://openalex.org/W2091528902","https://openalex.org/W2110228421","https://openalex.org/W2123905227","https://openalex.org/W2134963470","https://openalex.org/W2153829097","https://openalex.org/W2159247054","https://openalex.org/W3142992969","https://openalex.org/W4254533759","https://openalex.org/W6673590861"],"related_works":["https://openalex.org/W631083485","https://openalex.org/W184826316","https://openalex.org/W4313452936","https://openalex.org/W3132573772","https://openalex.org/W2097026685","https://openalex.org/W2480068220","https://openalex.org/W2070883797","https://openalex.org/W4386859288","https://openalex.org/W2102542442","https://openalex.org/W1986220761"],"abstract_inverted_index":{"In":[0,28,99],"the":[1,14,21,29,43,133,154,165,170,187,203],"field":[2],"of":[3,17,31,38,45,52,72,88,111,121,128,143,167,172,181,189,191,200,205],"chip":[4,18],"design,":[5],"hardware":[6],"module":[7,34],"reuse":[8],"is":[9,56,92],"a":[10,32,77,83,90,96,104,125,136,162,184],"standard":[11],"solution":[12],"to":[13,23,26,69,94],"increasing":[15],"complexity":[16],"architecture":[19],"and":[20,139,153,183],"pressures":[22],"reduce":[24],"time":[25],"market.":[27],"absence":[30],"single":[33,78],"interface":[35],"standard,":[36],"integration":[37],"pre-designed":[39],"modules":[40],"often":[41],"requires":[42],"use":[44],"protocol":[46,73,114,157],"converters.":[47,115],"For":[48],"an":[49,178,197],"arbitrary":[50],"pair":[51,127],"incompatible":[53,129],"protocols":[54,149],"it":[55],"likely":[57],"that":[58],"there":[59],"exist":[60],"more":[61],"than":[62],"one":[63],"possible":[64],"converter.":[65,98],"However,":[66],"existing":[67],"approaches":[68],"automatic":[70],"synthesis":[71],"converters":[74,123,146],"either":[75],"produce":[76],"suggested":[79],"converter":[80,171],"or":[81],"provide":[82],"general":[84],"nondeterministic":[85],"solution,":[86],"out":[87],"which":[89],"designer":[91],"required":[93],"extract":[95],"deterministic":[97],"this":[100],"work":[101],"we":[102],"present":[103,117],"novel":[105],"approach":[106],"for":[107,119,124,147],"design":[108,206],"space":[109,207],"exploration":[110],"FSM":[112],"based":[113],"We":[116,131],"algorithms":[118],"extraction":[120],"minimal":[122],"given":[126],"protocols.":[130],"demonstrate":[132],"process":[134],"through":[135],"simple":[137],"example,":[138],"report":[140],"on":[141],"results":[142],"experiments":[144,160],"with":[145],"commercial":[148],"AMBA":[150],"ASB,":[151],"APB":[152],"open":[155],"core":[156],"(OCP).":[158],"The":[159],"show":[161],"reduction":[163,180,185,199],"in":[164,169,186],"number":[166,188],"states":[168],"as":[173,175,192,194],"much":[174,193],"62%":[176],"(with":[177,196],"average":[179,198],"42%)":[182],"transitions":[190],"85%":[195],"61%),":[201],"demonstrating":[202],"benefits":[204],"exploration.":[208]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
