{"id":"https://openalex.org/W3142269918","doi":"https://doi.org/10.1109/date.2009.5090638","title":"Masking timing errors on speed-paths in logic circuits","display_name":"Masking timing errors on speed-paths in logic circuits","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W3142269918","doi":"https://doi.org/10.1109/date.2009.5090638","mag":"3142269918"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059471428","display_name":"Mihir Choudhury","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.R. Choudhury","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021693439","display_name":"Kartik Mohanram","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Mohanram","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74775410"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"87","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7079454660415649},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.6967014074325562},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6227786540985107},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5665839314460754},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5499836206436157},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.528039813041687},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.4590737819671631},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4392615258693695},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4136985242366791},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.41036486625671387},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2878207862377167},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.212770015001297},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16086360812187195},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14847001433372498}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7079454660415649},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.6967014074325562},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6227786540985107},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5665839314460754},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5499836206436157},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.528039813041687},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.4590737819671631},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4392615258693695},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4136985242366791},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.41036486625671387},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2878207862377167},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.212770015001297},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16086360812187195},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14847001433372498},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4699999988079071,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W147650083","https://openalex.org/W1970806136","https://openalex.org/W2047207707","https://openalex.org/W2084585992","https://openalex.org/W2089068515","https://openalex.org/W2104091244","https://openalex.org/W2104402818","https://openalex.org/W2110722301","https://openalex.org/W2118743217","https://openalex.org/W2119708813","https://openalex.org/W2121618685","https://openalex.org/W2125169487","https://openalex.org/W2125549312","https://openalex.org/W2133687702","https://openalex.org/W2141565132","https://openalex.org/W2142295179","https://openalex.org/W2146410479","https://openalex.org/W2156628821","https://openalex.org/W2161957517","https://openalex.org/W2168098726","https://openalex.org/W2169281837","https://openalex.org/W2971174528","https://openalex.org/W4231523873","https://openalex.org/W4236432903","https://openalex.org/W4239974125","https://openalex.org/W4248445118","https://openalex.org/W4254897134","https://openalex.org/W6605987033","https://openalex.org/W6672619538","https://openalex.org/W6675585046"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W2041787842"],"abstract_inverted_index":{"There":[0],"is":[1,48,137],"a":[2,26,45,53],"growing":[3],"concern":[4],"about":[5],"timing":[6,32,62,125],"errors":[7,33,126],"resulting":[8],"from":[9,107],"design":[10],"marginalities":[11],"and":[12,92,105],"the":[13,42,65,81,88,108,116,119,133],"effects":[14],"of":[15,44,52,90,118,124,132,148],"circuit":[16,47,56,71],"aging":[17],"on":[18,34,127],"speed-paths":[19,35,82,129],"in":[20,36,95],"logic":[21,37,46,67],"circuits.":[22,38],"This":[23],"paper":[24],"presents":[25],"low":[27],"overhead":[28,147],"solution":[29],"for":[30,101,139],"masking":[31,40,123],"Error":[39],"at":[41,59],"outputs":[43],"achieved":[49,138],"by":[50],"synthesis":[51],"non-intrusive":[54],"error-masking":[55,70],"that":[57],"has":[58],"least":[60],"20%":[61],"slack":[63],"over":[64],"original":[66],"circuit.":[68],"The":[69],"can":[72],"also":[73],"be":[74],"used":[75],"to":[76,85,114],"collect":[77],"runtime":[78],"information":[79],"when":[80],"are":[83,112],"exercised":[84],"(i)":[86],"predict":[87],"onset":[89],"wearout":[91],"(ii)":[93],"assist":[94],"in-system":[96],"silicon":[97],"debug.":[98],"Simulation":[99],"results":[100],"several":[102],"benchmark":[103],"circuits":[104,141],"modules":[106],"OpenSPARC":[109],"T1":[110],"processor":[111],"presented":[113],"illustrate":[115],"effectiveness":[117],"proposed":[120],"solution.":[121],"100%":[122],"all":[128,140],"within":[130],"10%":[131],"critical":[134],"path":[135],"delay":[136],"with":[142],"an":[143],"average":[144],"area":[145],"(power)":[146],"16%":[149],"(18%).":[150]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
