{"id":"https://openalex.org/W4237916382","doi":"https://doi.org/10.1109/date.2009.5090629","title":"An ILP formulation for task mapping and scheduling on multi-core architectures","display_name":"An ILP formulation for task mapping and scheduling on multi-core architectures","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W4237916382","doi":"https://doi.org/10.1109/date.2009.5090629"},"language":"en","primary_location":{"id":"doi:10.1109/date.2009.5090629","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042169991","display_name":"Yi Ying","orcid":"https://orcid.org/0000-0002-8658-3838"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Ying Yi","raw_affiliation_strings":["University of Edinburgh, Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052469808","display_name":"Wei Han","orcid":"https://orcid.org/0000-0002-0920-1357"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wei Han","raw_affiliation_strings":["University of Edinburgh, Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100445703","display_name":"Xin Zhao","orcid":"https://orcid.org/0000-0002-1276-5858"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Xin Zhao","raw_affiliation_strings":["University of Edinburgh, Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001069449","display_name":"Ahmet T. Erdogan","orcid":"https://orcid.org/0000-0003-2451-9395"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A.T. Erdogan","raw_affiliation_strings":["University of Edinburgh, Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022272531","display_name":"Tughrul Arslan","orcid":"https://orcid.org/0000-0001-8176-5803"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"T. Arslan","raw_affiliation_strings":["University of Edinburgh, Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.4128,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.8993187,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"38"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8539431095123291},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.626788318157196},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6083516478538513},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5859047174453735},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.5410991311073303},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5102555751800537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4905535578727722},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.4758146405220032},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.44633516669273376},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.44611692428588867},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4423680603504181},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.4234589636325836},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08882629871368408}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8539431095123291},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.626788318157196},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6083516478538513},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5859047174453735},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.5410991311073303},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5102555751800537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4905535578727722},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.4758146405220032},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44633516669273376},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.44611692428588867},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4423680603504181},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.4234589636325836},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08882629871368408},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2009.5090629","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2009.5090629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Design, Automation & Test in Europe Conference & Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1994849426","https://openalex.org/W2050487400","https://openalex.org/W2097602901","https://openalex.org/W2148548948","https://openalex.org/W2154106283","https://openalex.org/W2162348754","https://openalex.org/W3141273791","https://openalex.org/W4232630775","https://openalex.org/W4234540284","https://openalex.org/W4246270699"],"related_works":["https://openalex.org/W2041848531","https://openalex.org/W2276000909","https://openalex.org/W1646292588","https://openalex.org/W2139075651","https://openalex.org/W2963830067","https://openalex.org/W2134920996","https://openalex.org/W2940837694","https://openalex.org/W1547865754","https://openalex.org/W4255057712","https://openalex.org/W2067354926"],"abstract_inverted_index":{"Multi-core":[0],"architectures":[1,85],"are":[2,20,69],"increasingly":[3],"being":[4],"adopted":[5],"in":[6],"the":[7,39,73,96,109],"design":[8],"of":[9,16,79,105],"emerging":[10],"complex":[11],"embedded":[12],"systems.":[13],"Key":[14],"issues":[15],"designing":[17],"such":[18],"systems":[19],"on-chip":[21],"interconnects,":[22],"memory":[23,58],"architecture,":[24,112],"and":[25,28,42,57],"task":[26,40,51,53],"mapping":[27,41,62],"scheduling.":[29],"This":[30],"paper":[31],"presents":[32],"an":[33],"integer":[34],"linear":[35],"programming":[36],"formulation":[37],"for":[38],"scheduling":[43],"problem.":[44],"The":[45,92],"technique":[46,74,98],"incorporates":[47],"profiling-driven":[48],"loop":[49],"level":[50],"partitioning,":[52],"transformations,":[54],"functional":[55],"pipelining,":[56],"architecture":[59],"aware":[60],"data":[61],"to":[63,71,101,115],"reduce":[64],"system":[65],"execution":[66],"time.":[67],"Experiments":[68],"conducted":[70],"evaluate":[72],"by":[75,119],"implementing":[76],"a":[77],"series":[78],"DSP":[80],"applications":[81,107],"on":[82,87,108],"several":[83],"multi-core":[84,111],"based":[86],"dynamically":[88,123],"reconfigurable":[89,124],"processor":[90,125],"cores.":[91,126],"results":[93],"demonstrate":[94],"that":[95],"proposed":[97],"is":[99],"able":[100],"generate":[102],"high-quality":[103],"mappings":[104],"realistic":[106],"target":[110],"achieving":[113],"up":[114],"1.3times":[116],"parallel":[117],"efficiency":[118],"employing":[120],"only":[121],"two":[122]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}