{"id":"https://openalex.org/W4233104106","doi":"https://doi.org/10.1109/date.2008.4484915","title":"Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology","display_name":"Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W4233104106","doi":"https://doi.org/10.1109/date.2008.4484915"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484915","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100364291","display_name":"Xiaoying Wang","orcid":"https://orcid.org/0000-0002-2436-0807"},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Xiaoying Wang","raw_affiliation_strings":["Institute of Computer Science, University of Frankfurt am Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038049766","display_name":"Lars Hedrich","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lars Hedrich","raw_affiliation_strings":["Institute of Computer Science, University of Frankfurt am Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6304262,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"800","last_page":"803"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8181737661361694},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.73406982421875},{"id":"https://openalex.org/keywords/quadrant","display_name":"Quadrant (abdomen)","score":0.6452940702438354},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.6038765907287598},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5501585006713867},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4861176013946533},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.32387590408325195},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.32264894247055054},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17793315649032593},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.06899306178092957},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.05647650361061096}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8181737661361694},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.73406982421875},{"id":"https://openalex.org/C2780639617","wikidata":"https://www.wikidata.org/wiki/Q6516972","display_name":"Quadrant (abdomen)","level":2,"score":0.6452940702438354},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.6038765907287598},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5501585006713867},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4861176013946533},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.32387590408325195},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.32264894247055054},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17793315649032593},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.06899306178092957},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.05647650361061096},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2008.4484915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484915","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1999357165","https://openalex.org/W2096249093","https://openalex.org/W2109292497","https://openalex.org/W2141776905","https://openalex.org/W2169944292"],"related_works":["https://openalex.org/W2089088242","https://openalex.org/W2145104756","https://openalex.org/W2343687813","https://openalex.org/W2113697565","https://openalex.org/W1798980771","https://openalex.org/W4281295723","https://openalex.org/W2760424941","https://openalex.org/W1965508384","https://openalex.org/W2997198572","https://openalex.org/W2117233677"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,14],"method":[4],"towards":[5],"automatic":[6],"structural":[7],"synthesis":[8],"of":[9,39,47,71],"analog":[10],"multiplier":[11,62],"based":[12],"on":[13],"hierarchical":[15],"topology":[16],"\"super-topology\",":[17],"which":[18,37],"is":[19],"abstracted":[20],"from":[21],"the":[22,31,69],"most":[23],"standard":[24],"four-quadrant":[25],"multipliers.":[26,48],"The":[27],"essential":[28],"components":[29],"in":[30],"super-topology":[32],"are":[33],"four":[34],"identical":[35],"cells,":[36],"consist":[38],"several":[40],"MOS-transistors":[41],"and":[42,45],"determine":[43],"features":[44],"performances":[46],"We":[49],"build":[50],"all":[51],"possible":[52],"cells":[53],"within":[54],"3":[55],"transistors.":[56],"Experimental":[57],"results":[58,66],"present":[59],"three":[60],"new":[61],"structures":[63],"with":[64],"simulation":[65],"to":[67],"show":[68],"creativity":[70],"our":[72],"method.":[73]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
