{"id":"https://openalex.org/W3140003742","doi":"https://doi.org/10.1109/date.2008.4484810","title":"Compositional, dynamic cache management for embedded chip multiprocessors","display_name":"Compositional, dynamic cache management for embedded chip multiprocessors","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W3140003742","doi":"https://doi.org/10.1109/date.2008.4484810","mag":"3140003742"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484810","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089717134","display_name":"Anca Molnos","orcid":null},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Anca M. Molnos","raw_affiliation_strings":["NXP Semiconductors Corporate I and T, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors Corporate I and T, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055731407","display_name":"M.J.M. Heijligers","orcid":null},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Marc J.M. Heijligers","raw_affiliation_strings":["NXP Semiconductors Corporate I and T, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors Corporate I and T, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057424352","display_name":"Sorin Cot\u00f6fan\u0103","orcid":"https://orcid.org/0000-0001-7132-2291"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Sorin D. Cotofana","raw_affiliation_strings":["Technical University Delft, Delft, Netherlands"],"affiliations":[{"raw_affiliation_string":"Technical University Delft, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089717134"],"corresponding_institution_ids":["https://openalex.org/I109147379"],"apc_list":null,"apc_paid":null,"fwci":0.2727,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56640625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"991","last_page":"996"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8846920728683472},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8281121253967285},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6363614797592163},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5824275016784668},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5542511343955994},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.538234531879425},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.5266095399856567},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.5174813270568848},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4980897903442383},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.48437556624412537},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.41699743270874023},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.41481852531433105},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3293938636779785},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2539079785346985}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8846920728683472},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8281121253967285},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6363614797592163},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5824275016784668},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5542511343955994},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.538234531879425},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.5266095399856567},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.5174813270568848},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4980897903442383},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.48437556624412537},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.41699743270874023},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.41481852531433105},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3293938636779785},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2539079785346985},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2008.4484810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484810","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W22221353","https://openalex.org/W1490422487","https://openalex.org/W1606766658","https://openalex.org/W1967474856","https://openalex.org/W2011039300","https://openalex.org/W2096329363","https://openalex.org/W2098933180","https://openalex.org/W2115078506","https://openalex.org/W2155266777","https://openalex.org/W2157134596","https://openalex.org/W2172172009","https://openalex.org/W4231730792","https://openalex.org/W6600936453","https://openalex.org/W6629467423","https://openalex.org/W6674760637","https://openalex.org/W6677397167"],"related_works":["https://openalex.org/W2161101294","https://openalex.org/W2026179701","https://openalex.org/W2148571123","https://openalex.org/W4312759433","https://openalex.org/W2108638805","https://openalex.org/W4380881125","https://openalex.org/W2102608614","https://openalex.org/W2152423944","https://openalex.org/W2184371594","https://openalex.org/W273173017"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,25,45,57,109],"dynamic":[4,104],"cache":[5,26,66,105,140,172],"repartitioning":[6,21],"technique":[7],"that":[8,72],"enhances":[9,195],"compositionality":[10],"on":[11,108,143],"platforms":[12],"executing":[13],"media":[14],"applications":[15],"with":[16,52,112,186,196,200],"multiple":[17,129],"utilization":[18],"scenarios.":[19],"The":[20,116],"among":[22],"scenarios":[23],"requires":[24],"flush,":[27,87],"thus":[28],"two":[29],"undesired":[30],"effects":[31,54],"may":[32,40],"occur:":[33],"(1)":[34,60,146],"the":[35,65,75,83,96,138,147,160,170,181,189,201],"execution":[36,153],"of":[37,68,85,120,125,150],"critical":[38,78,151],"tasks":[39,79,130,152],"be":[41],"disturbed":[42],"and":[43,81,88,93,179,188],"(2)":[44,89,164],"performance":[46,190],"penalty":[47],"is":[48,174],"involved.":[49],"To":[50],"cope":[51],"these":[53,91],"we":[55,141],"propose":[56],"method":[58],"which:":[59],"determines,":[61],"at":[62,99,175],"design":[63],"time,":[64],"footprint":[67],"each":[69,124],"task,":[70],"such":[71],"it":[73],"creates":[74],"premises":[76],"for":[77,165],"safety,":[80],"reduces":[82,185],"amount":[84],"required":[86],"enforces":[90],"footprints":[92],"further":[94],"decreases":[95],"flush":[97],"penalty,":[98],"run-time.":[100],"We":[101],"implement":[102],"our":[103],"management":[106],"strategy":[107],"CAKE":[110],"multiprocessor":[111],"4":[113],"Trimedia":[114],"cores.":[115],"experimental":[117],"workload":[118],"consists":[119],"6":[121],"multimedia":[122],"applications,":[123],"which":[126],"formed":[127],"by":[128],"belonging":[131],"to":[132],"an":[133],"extended":[134],"MediaBench":[135],"suite.":[136],"For":[137],"repartitioned":[139],"found":[142],"average":[144],"that:":[145],"relative":[148],"variations":[149],"time":[154],"are":[155],"less":[156],"than":[157],"0.1%,":[158],"regardless":[159],"scenario":[161,167],"switching":[162,168],"frequency,":[163],"realistic":[166],"frequencies":[169],"inter-task":[171],"interference":[173],"most":[176],"4%":[177],",":[178],"(3)":[180],"off-chip":[182],"memory":[183],"traffic":[184],"60%,":[187],"(in":[191],"cycles":[192],"per":[193],"instructions)":[194],"10%,":[197],"when":[198],"compared":[199],"shared":[202],"cache.":[203]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}