{"id":"https://openalex.org/W3143757450","doi":"https://doi.org/10.1109/date.2008.4484789","title":"Approximate logic circuits for low overhead, non-intrusive concurrent error detection","display_name":"Approximate logic circuits for low overhead, non-intrusive concurrent error detection","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W3143757450","doi":"https://doi.org/10.1109/date.2008.4484789","mag":"3143757450"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484789","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059471428","display_name":"Mihir Choudhury","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mihir R. Choudhury","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021693439","display_name":"Kartik Mohanram","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kartik Mohanram","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74775410"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"903","last_page":"908"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7576299905776978},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7406759858131409},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6761125922203064},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.598168671131134},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.563322126865387},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5443408489227295},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42185163497924805},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.41699764132499695},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.41469606757164},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3533160090446472},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32599419355392456},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3204679489135742},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12921932339668274},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08703231811523438}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7576299905776978},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7406759858131409},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6761125922203064},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.598168671131134},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.563322126865387},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5443408489227295},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42185163497924805},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.41699764132499695},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.41469606757164},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3533160090446472},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32599419355392456},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3204679489135742},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12921932339668274},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08703231811523438},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2008.4484789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484789","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1578592046","https://openalex.org/W2047207707","https://openalex.org/W2084574629","https://openalex.org/W2084585992","https://openalex.org/W2104122494","https://openalex.org/W2123949947","https://openalex.org/W2125169487","https://openalex.org/W2133687702","https://openalex.org/W2137211463","https://openalex.org/W2147897801","https://openalex.org/W2156465872","https://openalex.org/W2971174528","https://openalex.org/W3149544844"],"related_works":["https://openalex.org/W1553855433","https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2789349722","https://openalex.org/W2170504327","https://openalex.org/W2766377030","https://openalex.org/W2102927888","https://openalex.org/W2326871975"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3],"scalable,":[4],"technology-independent":[5],"algorithm":[6,52],"for":[7,19,53],"the":[8,46],"synthesis":[9,51],"of":[10],"approximate":[11,36,54],"logic":[12,37,55],"circuits.":[13],"A":[14],"low":[15],"overhead,":[16],"non-intrusive":[17],"solution":[18],"concurrent":[20],"error":[21],"detection":[22],"(CED)":[23],"based":[24,34],"on":[25,35,45],"such":[26],"circuits":[27,38,56],"is":[28],"described":[29],"in":[30],"this":[31],"paper.":[32],"CED":[33,69],"does":[39],"not":[40],"impose":[41],"any":[42],"performance":[43],"penalty":[44],"original":[47],"design.":[48],"The":[49],"proposed":[50],"scales":[57],"with":[58],"circuit":[59],"size,":[60],"and":[61,68],"provides":[62],"fine-grained":[63],"trade-offs":[64],"between":[65],"area-power":[66],"overhead":[67],"coverage.":[70]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}