{"id":"https://openalex.org/W3148828450","doi":"https://doi.org/10.1109/date.2008.4484756","title":"Efficient Implementation of Native Software Simulation for MPSoC","display_name":"Efficient Implementation of Native Software Simulation for MPSoC","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W3148828450","doi":"https://doi.org/10.1109/date.2008.4484756","mag":"3148828450"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484756","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113765673","display_name":"Patrice Gerin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Patrice Gerin","raw_affiliation_strings":["System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041600862","display_name":"Xavier Gu\u00e9rin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Xavier Guerin","raw_affiliation_strings":["System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113546155","display_name":"Frederic Petrot","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Frederic Petrot","raw_affiliation_strings":["System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System-Level Synthesis Group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"676","last_page":"681"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9191796779632568},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8505550622940063},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8236294984817505},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6436408162117004},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6368386745452881},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.6243816614151001},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.4992866516113281},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4986870288848877},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47623518109321594},{"id":"https://openalex.org/keywords/embedded-software","display_name":"Embedded software","score":0.4714665710926056},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.44617563486099243},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4432353675365448},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4392220675945282},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16134268045425415},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07185286283493042}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9191796779632568},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8505550622940063},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8236294984817505},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6436408162117004},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6368386745452881},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6243816614151001},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.4992866516113281},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4986870288848877},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47623518109321594},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.4714665710926056},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.44617563486099243},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4432353675365448},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4392220675945282},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16134268045425415},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07185286283493042},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2008.4484756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484756","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00288336v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00288336","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Design Automation and Test in Europe (DATE'08), Mar 2008, Munich, Germany. pp.676-681, ⟨10.1109/DATE.2008.4484756⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1498455513","https://openalex.org/W2088983481","https://openalex.org/W2097521061","https://openalex.org/W2128093174","https://openalex.org/W2140755459","https://openalex.org/W2155867784","https://openalex.org/W2155900476","https://openalex.org/W4231198768","https://openalex.org/W4234507875","https://openalex.org/W4238272352","https://openalex.org/W4243988216","https://openalex.org/W4247732906","https://openalex.org/W4255682579","https://openalex.org/W6641838138"],"related_works":["https://openalex.org/W1934552808","https://openalex.org/W2293483919","https://openalex.org/W1976012348","https://openalex.org/W4230458348","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W3198758847","https://openalex.org/W4387782849","https://openalex.org/W2137671689","https://openalex.org/W1581055755"],"abstract_inverted_index":{"Efficient":[0],"and":[1,19,91,101],"precise":[2],"simulation":[3,31,62,87],"models":[4,97],"at":[5],"a":[6,53,78],"high":[7],"abstraction":[8],"level":[9],"are":[10],"required":[11],"in":[12],"order":[13],"to":[14,45,127],"perform":[15],"early":[16],"design":[17],"validations":[18],"architecture":[20,43],"explorations":[21],"of":[22,66,74,88,110,123],"multi-":[23],"processor":[24],"system-on-chip":[25],"(MPSoC)":[26],"platforms.":[27],"Although":[28],"native":[29,60],"software":[30,61,92,112,129],"approaches":[32],"provide":[33],"interesting":[34],"capabilities,":[35],"they":[36],"quickly":[37],"become":[38],"unsuitable":[39],"when":[40],"complex":[41,95,131],"hardware":[42,69,96,132],"have":[44],"be":[46],"considered.":[47],"In":[48],"this":[49,75],"paper,":[50],"we":[51],"present":[52],"SystemC-based":[54],"MPSoC":[55],"platform":[56],"implementation":[57],"that":[58,83],"allows":[59,107],"while":[63],"keeping":[64],"details":[65],"the":[67,86,108,115,121,124],"underlying":[68],"model.":[70],"The":[71],"key":[72],"contribution":[73],"work":[76],"is":[77],"realistic":[79],"memory":[80],"mapping":[81],"modelling":[82],"makes":[84],"possible":[85],"operating":[89],"systems":[90],"applications":[93],"on":[94,130],"with":[98],"multiple":[99],"processors":[100],"DMA":[102],"devices.":[103],"This":[104],"method":[105,126],"also":[106],"reuse":[109],"different":[111],"components":[113],"for":[114],"target":[116],"processor(s).":[117],"Experimental":[118],"results":[119],"show":[120],"efficiency":[122],"proposed":[125],"validate":[128],"architectures.":[133]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}