{"id":"https://openalex.org/W3152022554","doi":"https://doi.org/10.1109/date.2008.4484724","title":"Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction","display_name":"Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W3152022554","doi":"https://doi.org/10.1109/date.2008.4484724","mag":"3152022554"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484724","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041100073","display_name":"Anshuman Chandra","orcid":"https://orcid.org/0000-0002-2686-3918"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anshuman Chandra","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033924683","display_name":"Felix Ng","orcid":"https://orcid.org/0000-0002-7279-5370"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Felix Ng","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112339854","display_name":"Rohit Kapur","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rohit Kapur","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.9394,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.74995112,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"462","last_page":"467"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7225600481033325},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.7066674828529358},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6758368611335754},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6678632497787476},{"id":"https://openalex.org/keywords/volume","display_name":"Volume (thermodynamics)","score":0.5812097787857056},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5774821043014526},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5533890724182129},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.5322888493537903},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5129725337028503},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.4534705579280853},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.43404027819633484},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.42458394169807434},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39073917269706726},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3789823651313782},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3706684410572052},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3249998092651367},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2731459140777588},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25371256470680237},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2444503903388977},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21283552050590515},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.16832879185676575},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14137813448905945},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.11583414673805237},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0792069137096405}],"concepts":[{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7225600481033325},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.7066674828529358},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6758368611335754},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6678632497787476},{"id":"https://openalex.org/C20556612","wikidata":"https://www.wikidata.org/wiki/Q4469374","display_name":"Volume (thermodynamics)","level":2,"score":0.5812097787857056},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5774821043014526},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5533890724182129},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.5322888493537903},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5129725337028503},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.4534705579280853},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.43404027819633484},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.42458394169807434},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39073917269706726},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3789823651313782},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3706684410572052},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3249998092651367},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2731459140777588},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25371256470680237},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2444503903388977},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21283552050590515},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.16832879185676575},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14137813448905945},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.11583414673805237},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0792069137096405},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2008.4484724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484724","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2080510479","https://openalex.org/W2126641963","https://openalex.org/W2135627440","https://openalex.org/W2139234345","https://openalex.org/W2149690470","https://openalex.org/W2153309099","https://openalex.org/W2157198810","https://openalex.org/W2160621850","https://openalex.org/W2169839635","https://openalex.org/W4243807552","https://openalex.org/W4249647124"],"related_works":["https://openalex.org/W1581610324","https://openalex.org/W2131499522","https://openalex.org/W2129124567","https://openalex.org/W2167571917","https://openalex.org/W2189059878","https://openalex.org/W3088373974","https://openalex.org/W2620614665","https://openalex.org/W2110102663","https://openalex.org/W2146547687","https://openalex.org/W2049913894"],"abstract_inverted_index":{"We":[0],"present":[1],"low":[2],"power":[3,10,25,94],"illinois":[4],"scan":[5,22,28,71],"architecture":[6,49],"(LPILS)":[7],"to":[8,65,89,97],"achieve":[9,87],"dissipation":[11,26,95],"and":[12,32,56,73,99],"test":[13,101],"data":[14,102],"volume":[15,103],"reduction,":[16],"simultaneously.":[17],"By":[18],"using":[19],"the":[20,41,45,53,66,70,74],"proposed":[21,48],"architecture,":[23],"dynamic":[24,93],"during":[27],"testing":[29],"in":[30,92],"registers":[31],"combinational":[33,61],"cells":[34,72],"can":[35,85],"be":[36],"significantly":[37],"reduced":[38],"without":[39],"modifying":[40],"clock":[42],"tree":[43],"of":[44,52],"design.":[46],"The":[47],"is":[50],"independent":[51],"ATPG":[54],"patterns":[55],"imposes":[57],"a":[58],"very":[59],"small":[60],"area":[62],"penalty":[63],"due":[64,96],"logic":[67],"added":[68],"between":[69],"CUT.":[75],"Experimental":[76],"results":[77],"for":[78],"two":[79],"industrial":[80],"circuits":[81],"show":[82],"that":[83],"we":[84],"simultaneously":[86],"up":[88],"47%":[90],"reduction":[91,104],"switching":[98],"10X":[100],"with":[105],"LPILS":[106],"over":[107],"basic":[108],"scan.":[109]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}