{"id":"https://openalex.org/W3150294762","doi":"https://doi.org/10.1109/date.2008.4484652","title":"A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip","display_name":"A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W3150294762","doi":"https://doi.org/10.1109/date.2008.4484652","mag":"3150294762"},"language":"en","primary_location":{"id":"doi:10.1109/date.2008.4484652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484652","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043169928","display_name":"J\u00e9r\u00f4me Cornet","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Jerome Cornet","raw_affiliation_strings":["Centre \u00c9quation-2, VERIMAG, Gieres, France","System Platforms Group, STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre \u00c9quation-2, VERIMAG, Gieres, France","institution_ids":["https://openalex.org/I4210156361"]},{"raw_affiliation_string":"System Platforms Group, STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069307391","display_name":"Florence Maraninchi","orcid":"https://orcid.org/0000-0003-0783-9178"},"institutions":[{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Florence Maraninchi","raw_affiliation_strings":["Centre \u00c9quation-2, VERIMAG, Gieres, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre \u00c9quation-2, VERIMAG, Gieres, France","institution_ids":["https://openalex.org/I4210156361"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031519437","display_name":"Laurent Maillet-Contoz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Laurent Maillet-Contoz","raw_affiliation_strings":["System Platforms Group, STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System Platforms Group, STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5043169928"],"corresponding_institution_ids":["https://openalex.org/I4210104693","https://openalex.org/I4210156361"],"apc_list":null,"apc_paid":null,"fwci":3.7909,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.94936709,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"14"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8767862319946289},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.6506235599517822},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5080115795135498},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4859375059604645},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4696974754333496},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.45496827363967896},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45370692014694214},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4454697072505951},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.43144264817237854},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39673492312431335},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30017852783203125}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8767862319946289},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.6506235599517822},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5080115795135498},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4859375059604645},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4696974754333496},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.45496827363967896},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45370692014694214},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4454697072505951},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.43144264817237854},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39673492312431335},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30017852783203125},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2008.4484652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2008.4484652","pdf_url":null,"source":{"id":"https://openalex.org/S4363607582","display_name":"2008 Design, Automation and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Design, Automation and Test in Europe","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00281589v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00281589","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Design, Automation and Test in Europe, 2008. DATE '08, Mar 2008, Munich, Germany. pp.9 - 14, &#x27E8;10.1109/DATE.2008.4484652&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2136770003","https://openalex.org/W2150408604","https://openalex.org/W2169994946"],"related_works":["https://openalex.org/W1581055755","https://openalex.org/W2388040150","https://openalex.org/W2149449165","https://openalex.org/W4230718388","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W1869483461","https://openalex.org/W1491441517","https://openalex.org/W2399082377","https://openalex.org/W2140311261"],"abstract_inverted_index":{"Transaction":[0],"level":[1],"modeling":[2,115],"(TLM)":[3],"captures":[4],"abstract":[5,73],"models":[6,25,51,58,75,92,99],"of":[7,29,37,47],"systems-on-chip":[8],"that":[9],"simulate":[10],"faster":[11],"than":[12],"traditional":[13],"RTL":[14],"simulations":[15],"and":[16,56,77,113,120],"are":[17,52],"available":[18],"earlier":[19],"in":[20,49],"the":[21,27,30,38,41,88,98],"design":[22],"flow.":[23],"Such":[24],"allow":[26],"development":[28],"embedded":[31],"software":[32],"on":[33],"a":[34,63,68],"virtual":[35],"prototype":[36],"hardware,":[39],"before":[40],"chip":[42],"is":[43,62],"available.":[44],"Various":[45],"levels":[46],"details":[48],"TL":[50],"needed;":[53],"using":[54],"untimed":[55,74,119],"timed":[57,84,91,121],"for":[59,70,117],"different":[60],"purposes":[61],"usual":[64],"practice.":[65],"We":[66],"present":[67],"method":[69],"developing":[71],"very":[72],"first,":[76],"then":[78],"enriching":[79],"them":[80],"to":[81],"get":[82],"detailed":[83],"models,":[85],"while":[86],"preserving":[87],"functionality.":[89],"The":[90,104],"can":[93],"be":[94],"as":[95,97],"rich":[96],"usually":[100],"written":[101],"from":[102],"scratch.":[103],"experiments":[105],"with":[106],"industrial":[107],"case-studies":[108],"show":[109],"improved":[110],"simulation":[111],"speed":[112],"reduced":[114],"effort":[116],"both":[118],"models.":[122]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2025-10-10T00:00:00"}
