{"id":"https://openalex.org/W4234251677","doi":"https://doi.org/10.1109/date.2004.1269266","title":"Improving design and verification productivity with VHDL-200x","display_name":"Improving design and verification productivity with VHDL-200x","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W4234251677","doi":"https://doi.org/10.1109/date.2004.1269266"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1269266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269266","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054013312","display_name":"S. Bailey","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Bailey","raw_affiliation_strings":["Model Technology, Mentor Graphics Company, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Model Technology, Mentor Graphics Company, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050033237","display_name":"E. Marschner","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. Marschner","raw_affiliation_strings":["Cadence Design Systems, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052809542","display_name":"J. Bhasker","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100005","display_name":"Silicon Technologies (United States)","ror":"https://ror.org/013qwzt07","country_code":"US","type":"company","lineage":["https://openalex.org/I4210100005"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Bhasker","raw_affiliation_strings":["ESilicon Corporation, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ESilicon Corporation, USA","institution_ids":["https://openalex.org/I4210100005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016720099","display_name":"J. Lewis","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Lewis","raw_affiliation_strings":["SynthWorks, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SynthWorks, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038699575","display_name":"P. Ashenden","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Ashenden","raw_affiliation_strings":["Ashenden Designs Pty Limited, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ashenden Designs Pty Limited, Australia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.37254902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"332","last_page":"333"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.9239006638526917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6977591514587402},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5227755904197693},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.47108471393585205},{"id":"https://openalex.org/keywords/standardization","display_name":"Standardization","score":0.458998441696167},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4420568346977234},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3136948347091675},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19359007477760315},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.11703041195869446}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.9239006638526917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6977591514587402},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5227755904197693},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.47108471393585205},{"id":"https://openalex.org/C188087704","wikidata":"https://www.wikidata.org/wiki/Q369577","display_name":"Standardization","level":2,"score":0.458998441696167},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4420568346977234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3136948347091675},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19359007477760315},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.11703041195869446}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1269266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269266","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W2911649771","https://openalex.org/W2169179842","https://openalex.org/W2148697719","https://openalex.org/W2070083638"],"abstract_inverted_index":{"VHDL":[0,25,44,87,95,106,113,146],"is":[1,9,102,151,194],"a":[2,10,162,167],"critical":[3],"language":[4,31,60,164],"for":[5,26,49,69,88,104],"RTL":[6,17,27],"design":[7,28,38,70],"and":[8,41,97,159,178,181,187],"major":[11],"component":[12],"of":[13,144,169,184],"the":[14,30,80,94,105,112,128,133,145,205],"$200+":[15],"million":[16],"simulation":[18],"market.":[19],"Many":[20],"users":[21],"prefer":[22],"to":[23,33,72,74,120,127,153,174,196],"use":[24],"as":[29],"continues":[32],"provide":[34],"desired":[35],"characteristics":[36],"in":[37,62,76,86,139],"safety,":[39],"flexibility":[40],"maintainability.":[42],"While":[43],"has":[45,55,65],"provided":[46],"significant":[47,59],"value":[48,172],"digital":[50],"designers":[51],"since":[52],"1987,":[53],"it":[54,116],"had":[56],"only":[57],"one":[58],"revision":[61,150,193,208],"1993.":[63],"It":[64],"taken":[66],"many":[67],"years":[68,199],"state-of-practice":[71],"catch-up":[73],"and,":[75],"some":[77],"cases,":[78],"surpass":[79],"capabilities":[81],"that":[82,115],"have":[83],"been":[84],"available":[85],"over":[89],"15":[90],"years.":[91],"Last":[92],"year,":[93],"analysis":[96],"standardization":[98],"group":[99],"(VASG),":[100],"which":[101],"responsible":[103],"standard,":[107],"received":[108],"clear":[109],"indication":[110],"from":[111],"community":[114],"was":[117],"now":[118],"time":[119],"look":[121],"at":[122,140],"enhancing":[123],"VHDL.":[124],"In":[125],"response":[126],"user":[129,171],"community,":[130],"VASG":[131],"initiated":[132],"VHDL-200x":[134,136],"project.":[135],"will":[137,160],"result":[138],"least":[141],"two":[142],"revisions":[143],"standard.":[147],"The":[148],"first":[149],"planned":[152,195],"be":[154],"completed":[155],"next":[156],"year":[157],"(2004)":[158],"include":[161],"C":[163],"interface":[165],"(VHPI);":[166],"collection":[168],"high":[170],"enhancements":[173],"improve":[175],"designer":[176],"productivity":[177],"modeling":[179,189],"capability":[180],"potential":[182],"inclusion":[183],"assertion-based":[185],"verification":[186],"testbench":[188],"enhancements.":[190,209],"A":[191],"second":[192],"follow":[197],"about2":[198],"later.":[200],"This":[201],"paper":[202],"focuses":[203],"on":[204],"1/sup":[206],"st/":[207]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}