{"id":"https://openalex.org/W4243638536","doi":"https://doi.org/10.1109/date.2004.1269251","title":"A domain-specific cell based ASIC design methodology for digital signal processing applications","display_name":"A domain-specific cell based ASIC design methodology for digital signal processing applications","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W4243638536","doi":"https://doi.org/10.1109/date.2004.1269251"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1269251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269251","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033902886","display_name":"Baiyu Ren","orcid":"https://orcid.org/0000-0001-5106-7035"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Ren","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067601478","display_name":"Anni Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Wang","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039141663","display_name":"Joyopriya Bakshi","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Bakshi","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030784129","display_name":"K. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Liu","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100318407","display_name":"Wei Li","orcid":"https://orcid.org/0000-0003-2394-8745"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Li","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114859950","display_name":"W.W.-M. Dai","orcid":"https://orcid.org/0009-0007-6108-2547"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Dai","raw_affiliation_strings":["CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAD Laboratory, School of Engineering, University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6372,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72873638,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"280","last_page":"285"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.9555786848068237},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6924512982368469},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6567070484161377},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6294621229171753},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.48972561955451965},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.46779686212539673},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44910499453544617},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44678887724876404},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36674654483795166},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22677558660507202},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2153642773628235}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.9555786848068237},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6924512982368469},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6567070484161377},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6294621229171753},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.48972561955451965},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.46779686212539673},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44910499453544617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44678887724876404},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36674654483795166},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22677558660507202},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2153642773628235},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1269251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269251","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W115461275","https://openalex.org/W1882870471","https://openalex.org/W1941375539","https://openalex.org/W1994627436","https://openalex.org/W2011778848","https://openalex.org/W2103015818","https://openalex.org/W2126983197","https://openalex.org/W2138968074","https://openalex.org/W2168350974","https://openalex.org/W4232852482","https://openalex.org/W4256681489"],"related_works":["https://openalex.org/W2889102485","https://openalex.org/W2388299947","https://openalex.org/W2134697552","https://openalex.org/W4385831984","https://openalex.org/W3047211184","https://openalex.org/W2158494242","https://openalex.org/W2097839191","https://openalex.org/W4210376836","https://openalex.org/W2169589717","https://openalex.org/W2070693700"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"an":[3],"innovative":[4],"domain-specific":[5,55],"cell":[6,56,64],"based":[7,26],"ASIC":[8,20,27,45],"design":[9,21,28,35,46],"flow":[10,31],"to":[11,60,91],"narrow":[12],"the":[13,17,34,40,43,79,96,103],"performance":[14,36,93],"gap":[15],"between":[16],"full":[18],"custom":[19],"method":[22],"and":[23,37],"conventional":[24,104],"standard-cell":[25],"method.":[29],"The":[30],"can":[32,88],"improve":[33],"still":[38],"preserve":[39],"efficiency":[41],"of":[42,62,68],"standard":[44,63],"flow.":[47],"Targeting":[48],"on":[49,82],"digital":[50],"signal":[51],"processing":[52],"applications,":[53],"a":[54,85],"library":[57],"is":[58],"provided":[59],"augment":[61],"libraries.":[65],"Experimental":[66],"results":[67],"designing":[69],"macros":[70],"such":[71],"as":[72],"FFT,":[73],"FIR":[74],"etc.":[75],"are":[76],"shown":[77],"in":[78],"paper.":[80],"Based":[81],"this":[83],"methodology":[84],"64-tap":[86],"FFT":[87],"achieve":[89],"up":[90],"24X":[92],"improvement,":[94],"with":[95],"power/spl":[97],"times/delay/spl":[98],"times/area":[99],"(PDA)":[100],"criteria,":[101],"over":[102],"designed":[105],"ASICs.":[106]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
